Commit graph

248 commits

Author SHA1 Message Date
Kevin Lim
652281a61c Clean up clock phase drift code a bit.
src/cpu/base.cc:
    Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
    Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Use the function now in BaseCPU.

--HG--
extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
2006-11-06 13:27:45 -05:00
Kevin Lim
067c9c5531 Initialize pointer to NULL.
src/cpu/o3/lsq_unit_impl.hh:
    Be sure to initialize pointer to NULL.

--HG--
extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
2006-11-05 20:29:38 -05:00
Ali Saidi
de90ae4825 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : d7133e32cfca9f15869ee9ab7a93e3470e7d9038
2006-11-04 21:41:10 -05:00
Ali Saidi
21cf4a46b9 fixes so that M5 will compile under solaris
SConstruct:
    Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
    use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
    If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
    solaris doesn't have random(), so use rint with the correct rounding mode
    if we're compiling on solaris
src/base/stats/flags.hh:
    u_int32_t??
src/base/time.hh:
    grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
    we don't need to include stdint here
src/sim/byteswap.hh:
    the method to detect endianness on Solaris is a little more complex...

--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
2006-11-04 21:41:01 -05:00
Kevin Lim
e71ccde663 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
2006-11-02 15:20:47 -05:00
Kevin Lim
dd5e2cd959 More proper handling of the ports.
src/cpu/simple_thread.cc:
    Fix up port handling to share code.
src/cpu/thread_state.cc:
    Separate code off into a function.
src/cpu/thread_state.hh:
    Make a separate function that will get the CPU's memory's functional port.

--HG--
extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312
2006-11-02 14:58:31 -05:00
Kevin Lim
64f8cd12c6 Remove function that should have been deleted.
src/cpu/simple_thread.cc:
    This function should have been deleted from an earlier push.
src/cpu/simple_thread.hh:
    Delete this function; it's now in thread_state.hh/.cc.

--HG--
extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff
2006-11-02 13:12:36 -05:00
Kevin Lim
ccaf80cc46 Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
    For now makeExtMI will be specific to the ISA.

--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-11-02 13:11:38 -05:00
Gabe Black
b565660c42 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01 19:00:59 -05:00
Gabe Black
2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Kevin Lim
5825a6c9d8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31 14:37:19 -05:00
Kevin Lim
bfd5eb2b08 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    No need for mem parameter any more.
src/cpu/checker/cpu.cc:
    Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
    Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
    Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
    Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
    Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
    Remove memory parameter.

--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31 14:33:56 -05:00
Kevin Lim
b26355daa8 Ports now have a pointer to the MemObject that owns it (can be NULL).
src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31 13:59:30 -05:00
Gabe Black
3c19c5f0f2 Missed a few instances of this function.
--HG--
extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
2006-10-31 04:12:52 -05:00
Gabe Black
038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Gabe Black
4862879a94 Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
2006-10-31 02:08:44 -05:00
Gabe Black
628a3b1d01 An attempt to serialize the state of the micro code mechanism in the simple cpu.
src/cpu/simple/base.cc:
    Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
    Serialize the microPC and nextMicroPC

--HG--
extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
2006-10-29 04:04:50 -05:00
Gabe Black
ab6b6a9202 This one really needs to be arch/faults.hh
--HG--
extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
2006-10-28 04:44:05 -04:00
Gabe Black
7f1463f94a Include the right version of faults.hh
--HG--
extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
2006-10-28 04:00:24 -04:00
Gabe Black
27ef642a76 One last adjustment to get rid of skew in the simple atomic cpu.
--HG--
extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
2006-10-28 03:44:55 -04:00
Gabe Black
a46e19f738 A more complete attempt to fix the clock skew.
--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
2006-10-27 07:09:14 -04:00
Gabe Black
d5974eff73 Potential fix to clock skew problem.
--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
2006-10-27 06:51:28 -04:00
Lisa Hsu
764f27a0c9 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
2006-10-23 18:46:05 -04:00
Lisa Hsu
0a2387f38c make this parallel to the other cpu types so that resume works correctly.
--HG--
extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
2006-10-23 18:43:56 -04:00
Gabe Black
ef8b7713ca Minor compile fix. Not sure why this is broken.
--HG--
extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
2006-10-23 11:17:59 -04:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23 09:44:58 -04:00
Gabe Black
e9908e3c85 Don't let interupts interupt microcode at undesired points.
--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
2006-10-23 02:39:02 -04:00
Steve Reinhardt
0159529343 Add Quiesce trace flag to track CPU quiesce/wakeup events.
--HG--
extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
2006-10-21 23:32:14 -07:00
Gabe Black
0b5cf4ba6e Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
2006-10-20 16:39:47 -04:00
Ron Dreslinski
54ed57cc4c Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

src/mem/tport.cc:
    Merge PacketPtr changes

--HG--
extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20 13:04:59 -04:00
Ron Dreslinski
28e9641c2c Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
    Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
    Use fix Packet function
src/mem/packet.cc:
    Fix an assert that was checking the wrong thing
src/mem/tport.cc:
    Properly detect if we need to do the access to the functional device

--HG--
extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20 13:01:21 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Ron Dreslinski
cc1feb9f6d Fix memtester to use functional access, fix cache to work functionally now that we could test it.
src/cpu/memtest/memtest.cc:
    Fix memtest to do functional accesses
src/mem/cache/cache_impl.hh:
    Fix cache to handle functional accesses properly based on memtester changes
    Still need to fix functional accesses in timing mode now that the memtester can test it.

--HG--
extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
2006-10-19 21:07:53 -04:00
Ron Dreslinski
210e73f2a2 Small changes:
?? doesn't compile in warn statements
Should have been false, where I had a true.

src/cpu/o3/lsq_impl.hh:
    Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
    Forgot to signal atomic mode in snoopProbe

--HG--
extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19 20:18:17 -04:00
Ron Dreslinski
9cf063eb8e Merge zizzer:/bk/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19 19:00:43 -04:00
Gabe Black
bb2ab310eb Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
    Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
    Make floating point register numbers correlate to the numbers used in SPARC.

--HG--
extra : convert_revision : 878897292f696092453cf61d6eac2d1c407ca13b
2006-10-18 20:52:34 -04:00
Lisa Hsu
c2c48645c9 only do this assert after you know you're not switched out or idle.
--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
2006-10-18 17:59:11 -04:00
Ron Dreslinski
9c582c7e14 Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17 18:50:19 -04:00
Gabe Black
519d11bab3 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
2006-10-16 15:56:53 -04:00
Gabe Black
f1661baf30 Fix up microcode support.
src/arch/sparc/isa/formats/blockmem.isa:
    Several small and medium bug fixes.
src/cpu/simple/base.cc:
    Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
    Made sure the microPC and nextMicroPC are initialized properly.

--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
2006-10-16 15:56:46 -04:00
Gabe Black
333a7c4ba2 Started implementing microcode.
--HG--
extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690
2006-10-15 21:04:14 -04:00
Kevin Lim
a50e83c134 Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
    Move assertion to area where it should really always be true.  Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).

--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-13 17:35:23 -04:00
Lisa Hsu
339b1f8516 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

src/cpu/simple/timing.cc:
    hand merge

--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12 18:56:57 -04:00
Gabe Black
866dda9778 StaticInst support for microcode
--HG--
extra : convert_revision : c9e062637faf2166f0d36b914f3efa7f80626663
2006-10-12 17:32:02 -04:00
Ron Dreslinski
6ffdc7b4d7 Another memleak in the memtester (need [] with the delete)
src/cpu/memtest/memtest.cc:
    Another memleak in the memtester

--HG--
extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
2006-10-12 13:45:28 -04:00
Ron Dreslinski
dd18ffe51d Fix a memory leak in the memtester
--HG--
extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
2006-10-12 13:43:12 -04:00
Gabe Black
866cfaf9dc Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
2006-10-12 10:58:45 -04:00
Lisa Hsu
024b33a1ef some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
    memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
    some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.

--HG--
extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
2006-10-11 18:44:48 -04:00
Ron Dreslinski
567afbf6ce More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11 18:28:33 -04:00