ARM gem5 Developers
612f8f074f
arm: Add support for ARMv8 (AArch64 & AArch32)
...
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.
Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
2014-01-24 15:29:34 -06:00
Andreas Hansson
c10098f28b
scons: Fix up numerous warnings about name shadowing
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This patch address the most important name shadowing warnings (as
produced when using gcc/clang with -Wshadow). There are many
locations where constructor parameters and function parameters shadow
local variables, but these are left unchanged.
2013-02-19 05:56:06 -05:00
Gabe Black
d735abe5da
GCC: Get everything working with gcc 4.6.1.
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And by "everything" I mean all the quick regressions.
2011-10-31 01:09:44 -07:00
Ali Saidi
401165c778
ARM: Further break up condition code into NZ, C, V bits.
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Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
2011-05-13 17:27:01 -05:00
Ali Saidi
2178859b76
ARM: Break up condition codes into normal flags, saturation, and simd.
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This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
2011-05-13 17:27:01 -05:00
Ali Saidi
632cf8dd80
ARM: Fix small bug with vcvt instruction
2011-05-04 20:38:26 -05:00
Ali Saidi
b754ad85c0
ARM: Fix small bug with VLDM/VSTM instructions.
2011-03-17 19:20:20 -05:00
Matt Horsnell
adbd84ab9f
ARM: The ARM decoder should not panic when decoding undefined holes is arch.
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This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
2011-01-18 16:30:05 -06:00
Gabe Black
63464d950e
ARM: Seperate out the renamable bits in the FPSCR.
2010-08-25 19:10:42 -05:00
Gabe Black
6368edb281
ARM: Implement all ARM SIMD instructions.
2010-08-25 19:10:42 -05:00
Ali Saidi
fc1730044e
ARM: Decode neon memory instructions.
2010-08-23 11:18:40 -05:00
Gabe Black
85ba2a3243
ARM: Decode the neon instruction space.
2010-06-02 12:58:18 -05:00
Gabe Black
5a6bf8301a
ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.
2010-06-02 12:58:17 -05:00
Gabe Black
b93ceef538
ARM: Get rid of some of the old FP implementation.
2010-06-02 12:58:16 -05:00
Gabe Black
237c0617a0
ARM: Implement conversion to/from half precision.
2010-06-02 12:58:16 -05:00
Gabe Black
92bdf57be4
ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.
2010-06-02 12:58:15 -05:00
Gabe Black
2d08b8de91
ARM: Implement the version of VMRS that writes to the APSR.
2010-06-02 12:58:15 -05:00
Gabe Black
49b7088b91
ARM: Implement the VCMPE instruction.
2010-06-02 12:58:15 -05:00
Gabe Black
1b3b75ee68
ARM: Implement the version of VCVT float to int that rounds towards zero.
2010-06-02 12:58:15 -05:00
Gabe Black
aa05e5401c
ARM: Implement the floating/fixed point VCVT instructions.
2010-06-02 12:58:15 -05:00
Gabe Black
e478df35f5
ARM: Implement the VFP version of VCMP.
2010-06-02 12:58:14 -05:00
Gabe Black
c1f7bf7f0e
ARM: Add support for VFP vector mode.
2010-06-02 12:58:14 -05:00
Gabe Black
41012d2418
ARM: Implement VCVT between double and single width FP.
2010-06-02 12:58:14 -05:00
Gabe Black
a430f749ce
ARM: Implement vcvt between int and fp. Ignore rounding.
2010-06-02 12:58:14 -05:00
Gabe Black
a9d1de4769
ARM: Consolidate the VFP register index computation code.
2010-06-02 12:58:14 -05:00
Gabe Black
80fa3a7ccf
ARM: Implement the VFP negated multiplies.
2010-06-02 12:58:14 -05:00
Gabe Black
3111a62169
ARM: Implement the VFP versions of VMLA and VMLS.
2010-06-02 12:58:14 -05:00
Gabe Black
90d70a22cb
ARM: Implement the VFP version of vdiv and vsqrt.
2010-06-02 12:58:14 -05:00
Gabe Black
cc665240a4
ARM: Implement the VFP version of vsub.
2010-06-02 12:58:14 -05:00
Gabe Black
44759669aa
ARM: Implement the VFP version of vadd.
2010-06-02 12:58:14 -05:00
Gabe Black
9e32ff3491
ARM: Implement the VFP version of vabs.
2010-06-02 12:58:14 -05:00
Gabe Black
cd0a6a1303
ARM: Implement the VFP version of vneg.
2010-06-02 12:58:14 -05:00
Gabe Black
65f5204325
ARM: Implement the VFP version of vmul.
2010-06-02 12:58:14 -05:00
Gabe Black
19e05d7e8d
ARM: Move the VFP data operation decode into a function.
2010-06-02 12:58:14 -05:00
Gabe Black
81b7c3d264
ARM: Move the FP decode blocks into functions.
2010-06-02 12:58:13 -05:00
Gabe Black
2e4ddbd234
ARM: Decode the VSTR instruction.
2010-06-02 12:58:12 -05:00
Gabe Black
943b77b9bb
ARM: Decode the VLDR instruction.
2010-06-02 12:58:12 -05:00
Gabe Black
dbec303864
ARM: Decode all the various forms of vmov.
2010-06-02 12:58:12 -05:00
Gabe Black
6365d29c21
ARM: Decode the VMRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
a8b56b452c
ARM: Decode the VMSR instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
0ff71c7c34
ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
2010-06-02 12:58:11 -05:00
Gabe Black
3f83094af2
ARM: Decode the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
48525f581c
ARM: Split the condition codes out of the CPSR.
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This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
2a39570b78
ARM: Remove the currently unecessary FPAOp class.
2009-06-21 17:14:51 -07:00
Gabe Black
c20ce20e4c
ARM: Make the isa parser aware that CPSR is being used.
2009-06-21 09:37:41 -07:00
Gabe Black
71e0d1ded2
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 09:21:07 -07:00
Stephen Hines
7a7c4c5fca
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
