Commit graph

780 commits

Author SHA1 Message Date
Fernando Endo
6c72c35519 cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-15 14:58:45 -05:00
Andreas Hansson
2f5262eb67 config: Make configs/common a Python package
Continue along the same line as the recent patch that made the
Ruby-related config scripts Python packages and make also the
configs/common directory a package.

All affected config scripts are updated (hopefully).

Note that this change makes it apparent that the current organisation
and naming of the config directory and its subdirectories is rather
chaotic. We mix scripts that are directly invoked with scripts that
merely contain convenience functions. While it is not addressed in
this patch we should follow up with a re-organisation of the
config structure, and renaming of some of the packages.
2016-10-14 10:37:38 -04:00
Andreas Hansson
68fdccb30b ruby: Fix regressions and make Ruby configs Python packages
This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.

As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
2016-10-13 03:17:19 -04:00
Tushar Krishna
2e5e908579 config: fix typo in cluster topology. 2016-10-07 23:56:48 -04:00
Tushar Krishna
dbe8892b76 ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.
2016-10-06 14:35:22 -04:00
Tushar Krishna
0962d76827 config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.
2016-10-06 14:35:20 -04:00
Tushar Krishna
003c08fa90 config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
2016-10-06 14:35:18 -04:00
Tushar Krishna
b9e23a6d74 config: add a separate config file for the network.
This patch adds a new file configs/network/Network.py to setup the network,
instead of doing that within Ruby.py.
2016-10-06 14:35:17 -04:00
Tushar Krishna
0f68b50ff1 ruby: rename networktest to garnet_synthetic_traffic.
networktest is essentially a collection of synthetic traffic patterns
for the network. The protocol name and the tester having the same name
led to multiple python configuration files with the same name, adding
confusion. This patch renames networktest to garnet_synthetic_traffic,
and also adds more synthetic traffic patterns.
2016-10-06 14:35:16 -04:00
Tushar Krishna
aca869bf2d ruby: rename ALPHA_Network_test protocol to Garnet_standalone.
Over the past 6 years, we realized that the protocol is essentially used
to run the garnet network in a standalone manner, and feed standard synthetic
traffic patterns through it.
2016-10-06 14:35:14 -04:00
Andreas Hansson
b4b50f8230 config: Fix lat_mem_rd example script
Adjust the traffic generator time-out so that the script works out of
the box

Change-Id: I6b3b6b11f98b094ae3acdbe09488c26e4aeb0ab4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-10-04 15:44:52 +01:00
Gabor Dozsa
fb349aa984 arm, config: Fixups for the example big.LITTLE(tm) configuration
This patch refactors the configuration file to use a more
object-oriented design.

Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
2016-09-15 18:00:59 +01:00
Michael LeBeane
2068af5768 config: move dist-gem5 options to common config
dist-gem5 should not be restricted to FullSystem mode.
2016-09-13 23:16:06 -04:00
David Hashe
d1abc287f6 config: KVM acceleration for apu_se.py
Add support for using KVM to accelerate APU simulations. The intended use
case is to fast-forward through runtime initialization until the first
kernel launch.
2016-08-22 11:43:44 -04:00
Andreas Hansson
080d4e08d6 mem: Add snoop filter to SystemXBar by default
This patch changes the default behaviour of the SystemXBar, adding a
snoop filter. With the recent updates to the snoop filter allocation
behaviour this change no longer causes problems for the regressions
without caches.

Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12 14:11:45 +01:00
Andreas Sandberg
da07c5c26a arm, config: Exit with fatal error if using Ruby
Ruby on ARM is currently very experimental. Fail with a fatal error
that explains this to make sure users are aware of the limitations (it
doesn't actually work yet!).

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-10 16:40:14 +01:00
Andreas Sandberg
eb87ed8e74 arm, config: Add initial support for Ruby
Add initial support for creating an ARM system with a Ruby-based
memory system. This support is currently experimental and limited to
the new VExpress_GEM5_V1 platform.

Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10 16:26:34 +01:00
Andreas Sandberg
26dc0017d2 ruby: Implement support for functional accesses to PIO ranges
There are cases where we want to put boot ROMs on the PIO bus. Ruby
currently doesn't support functional accesses to such memories since
functional accesses are always assumed to go to physical memory. Add
the required support for routing functional accesses to the PIO bus.

Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>
2016-08-10 15:27:13 +01:00
Gabor Dozsa
a288c94387 arm, config: Add an example ARM big.LITTLE(tm) configuration script
An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-21 17:19:16 +01:00
Jakub Jermar
86a25bbcee config: Allow SPARC FS image to be specified on the command line
At the moment the SPARC FS machine configuration comes with a hardcoded
value for using the Solaris 10 disk image from the OpenSPARC tarball. The
--disk-image option is completely ignored for SPARC. This simple patch
modifies the behavior so that --disk-image option is both taken into
account and also required. This makes it possible to easily change SPARC FS
images without having to modify the configuration files.
2016-07-19 09:52:46 -05:00
Abdul Mutaal Ahmad
9c20880fb5 mem: tester for new HMC configuration
This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:48:43 -05:00
Abdul Mutaal Ahmad
7cb0c7bd65 mem: different HMC configuration
In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>
2016-07-01 09:45:21 -05:00
Andreas Hansson
2c91ccfbe8 config: Fix omission of walker cache in config scripts
This patch ensures a walker cache is instantiated if specfied.

Change-Id: I2c6b4bf3454d56bb19558c73b406e1875acbd986
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
2016-06-20 14:39:49 +01:00
jkalamat
3724fb15fa gpu-compute: parametrize Wavefront size
Eliminate the VSZ constant that defined the Wavefront size (in numbers of work
items); replaced it with a parameter in the GPU.py configuration script.
Changed all data structures dependent on the Wavefront size to be dynamically
sized. Legal values of Wavefront size are 16, 32, 64 for now and checked at
initialization time.
2016-06-09 11:24:55 -04:00
Stephan Diestelhorst
71a02f624e mem, config: Selective use of snoop filter
Disable the default snoop filter in the SystemXBar so that the
typical membus does not have a snoop filter by default. Instead,
add the snoop filter only when there are caches added to the system
(with the caches / l2cache options).

The underlying problem is that the snoop filter grows without
bounds (for now) if there are no caches to tell it that lines have
been evicted. This causes slow regression runs for all the atomic
regressions. This patch fixes this behaviour.

--HG--
extra : source : f97c20511828209757440839ed48d741d02d428f
2016-05-27 17:05:58 +01:00
Bjoern A. Zeeb
7fc668fae9 config, x86: Properly space pad the X86IntelMPBus Entry descriptions
According to the Intel Multi Processor Specification rev 1.4 (-006) (*),
section 4.3.2 Bus Entries, Bus type strings are >>6-character ASCII
(blank-filled) strings<<.
This patch properly pads the entries with the missing spaces at the end.

(*) http://www.intel.com/design/pentium/datashts/24201606.pdf

Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-05-19 15:19:35 -05:00
Andreas Hansson
53d735b17e config: Add missing point of coherency to memcheck script
Bring in line with changes to the XBar class.
2016-04-21 04:48:04 -04:00
Mohammad Alian
90cb9827be dist: config file for distributed switch
Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.
2016-04-14 14:07:42 -04:00
Andreas Hansson
48d07b3fa3 configs: Add a lat_mem_rd style test script
This patch adds a config script that broadly replicates the behaviour
of lat_mem_rd. The test is based on traffic generators, and as such we
simply randomise addresses in increasingly large ranges, and play them
back using the trace functionality of the traffic generator.

The test script is accompanied by a post-processing and visualisation
script. At the moment no configurability is added to tweak the memory
hierarchy, but a follow on patch could easily extend the
functionality.
2016-03-08 17:51:02 -05:00
Andreas Hansson
92f021cbbe mem: Move the point of coherency to the coherent crossbar
This patch introduces the ability of making the coherent crossbar the
point of coherency. If so, the crossbar does not forward packets where
a cache with ownership has already committed to responding, and also
does not forward any coherency-related packets that are not intended
for a downstream memory controller. Thus, invalidations and upgrades
are turned around in the crossbar, and the memory controller only sees
normal reads and writes.

In addition this patch moves the express snoop promotion of a packet
to the crossbar, thus allowing the downstream cache to check the
express snoop flag (as it should) for bypassing any blocking, rather
than relying on whether a cache is responding or not.
2016-02-10 04:08:25 -05:00
Andreas Hansson
fbdeb60316 mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.

The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
2016-02-10 04:08:24 -05:00
Steve Reinhardt
dc8018a5c3 style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06 17:21:18 -08:00
Brad Beckmann
97a5e5b25e ruby: changed all references to numCPs to num-cp 2016-01-22 10:42:12 -05:00
Tony Gutierrez
1a7d3f9fcb gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
Andreas Sandberg
745f8229f6 dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:

  * Automatic PCI interrupt assignment
  * PCI interrupts allocated in a contiguous range.
  * Automatic boot loader selection (32-bit / 64-bit)
  * Cleaner memory map where gem5-specific devices live in CS5 which
    isn't used by current Versatile Express platforms.
  * No fake devices. Devices that were previously faked will be
    removed from the device tree instead.
  * Support for 510 GiB contiguous memory
2016-01-15 11:30:13 +00:00
Andreas Hansson
c965ca96cc configs: Fix inheritance of HMCSystem and cleanup spacing
Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.
2016-01-11 05:52:17 -05:00
Gabor Dozsa
64ca31976f config: Updates for distributed gem5 simulations 2016-01-07 16:33:47 -06:00
Andreas Hansson
219f1c1a7f configs: Make the default memtest behaviour more complex
Add functional and uncacheable accesses by default.
2015-12-17 17:07:22 -05:00
Brad Beckmann
173a786921 ruby: more flexible ruby tester support
This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests.  This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code.  Finally, the patch also includes better DPRINTFs for
debugging the tester.
2015-07-20 09:15:18 -05:00
Radhika Jagtap
9bd5051b60 config: Enable elastic trace capture and replay in se/fs
This patch adds changes to the configuration scripts to support elastic
tracing and replay.

The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.

The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.
2015-12-07 16:42:16 -06:00
Andreas Sandberg
78275c9d2f dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.
2015-12-05 00:11:24 +00:00
Andreas Sandberg
6a05179e13 arm, config: Automatically discover available platforms
Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.
2015-12-04 00:19:05 +00:00
Andrew Bardsley
4375678a0d config: Added missing types to JSON/INI Python reader
Added the missing types EthernetAddr and Current to the JSON/INI file
reader example configs/example/read_config.py.

Also added __str__ to EthernetAddr to make values appear in the same form
in JSON an INI files.
2015-11-22 05:10:21 -05:00
Andreas Hansson
6adb728fb4 config: Minor fixes to the DRAM utilisation sweep 2015-11-22 05:10:17 -05:00
Andreas Hansson
337774e192 config: Update memtest to stress test clean writebacks
This patch adds yet another twist to the memtest cache hierarchy, in that
the writeback_clean option is toggled at every level to match the
clusivity of the downstream cache.
2015-11-06 03:26:44 -05:00
Andreas Hansson
7433d77fcf mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.

The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.

The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py
2015-11-06 03:26:43 -05:00
Andreas Hansson
afa252b0b9 config: Update memtest to stress test cache clusivity
This patch adds an new twist to the memtest cache hierarchy, in that
it switches from mostly inclusive to mostly exclusive at every level
in the tree. This has helped weed out plenty issues, and serves as a
good stress tests.
2015-11-06 03:26:42 -05:00
Andreas Hansson
654266f39c mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.

The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.

This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.

Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.

The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
2015-11-06 03:26:41 -05:00
Nilay Vaish
6433a10749 configs: fix bug introduced due to 276ad9121192
I had made a typo in changeset 276ad9121192.  This changeset fixes it
2015-11-04 12:36:28 -06:00
Erfan Azarkhish
100cbc9cf6 mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It
highly reuses the existing components in gem5's general memory system with some
small modifications. This changeset requires additional patches to model a
complete HMC device.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-03 12:17:56 -06:00