Commit graph

12 commits

Author SHA1 Message Date
Andrew Bardsley
0c001e729a dev: Fix IsaFake's cxx_header setting
cxx_header was set incorrectly on IsaFake
2014-03-23 11:11:37 -04:00
Andreas Sandberg
c0ab52799c sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
2012-11-02 11:32:01 -05:00
Andreas Hansson
cf5935445f Device: Bump PIO and PCI latencies to more reasonable values
This patch addresses a previously highlighted issue with the default
latencies used for PIO and PCI devices. The values are merely educated
guesses and might not represent the particular system you want to
model. However, the values in this patch are definitely far more
realistic than the previous ones.

In i8254xGBe, the writeConfig method is updated to use configDelay
instead of pioDelay.

A follow-up patch will update the regression stats.
2012-09-10 11:57:36 -04:00
Andreas Hansson
c60db56741 Packet: Remove NACKs from packet and its use in endpoints
This patch removes the NACK frrom the packet as there is no longer any
module in the system that issues them (the bridge was the only one and
the previous patch removes that).

The handling of NACKs was mostly avoided throughout the code base, by
using e.g. panic or assert false, but in a few locations the NACKs
were actually dealt with (although NACKs never occured in any of the
regressions). Most notably, the DMA port will now never receive a NACK
and the backoff time is thus never changed. As a consequence, the
entire backoff mechanism (similar to a PCI bus) is now removed and the
DMA port entirely relies on the bus performing the arbitration and
issuing a retry when appropriate. This is more in line with e.g. PCIe.

Surprisingly, this patch has no impact on any of the regressions. As
mentioned in the patch that removes the NACK from the bridge, a
follow-up patch should change the request and response buffer size for
at least one regression to also verify that the system behaves as
expected when the bridge fills up.
2012-08-22 11:39:59 -04:00
Andreas Hansson
70e99e0b91 Device: Remove overloaded pio_latency parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.

The PciConfigAll now also uses a Param.Latency rather than a
Param.Tick. For backwards compatibility it still sets the pio_latency
to 1 tick. All the comments have also been updated to not state that
it is in simticks when it is not necessarily the case.
2012-08-21 05:50:03 -04:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Gabe Black
c3d41a2def Merge with the main repo.
--HG--
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-28 07:24:01 -08:00
Andreas Hansson
55cf3f4ac1 MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.
2012-01-17 12:55:09 -06:00
Gabe Black
d368344092 SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
2011-10-04 02:26:03 -07:00
Ali Saidi
f8538f7456 IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
Steve Reinhardt
6629d9b2bc mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Nathan Binkert
35147170f9 Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

--HG--
rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py
rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py
rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py
rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py
rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py
rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py
rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py
rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py
rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py
rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py
rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py
rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py
rename : src/python/m5/objects/Device.py => src/dev/Device.py
rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py
rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py
rename : src/python/m5/objects/Ide.py => src/dev/Ide.py
rename : src/python/m5/objects/Pci.py => src/dev/Pci.py
rename : src/python/m5/objects/Platform.py => src/dev/Platform.py
rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py
rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py
rename : src/python/m5/objects/Uart.py => src/dev/Uart.py
rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py
rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py
rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py
rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py
rename : src/python/m5/objects/Bus.py => src/mem/Bus.py
rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py
rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py
rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py
rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py
rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py
rename : src/python/m5/objects/Process.py => src/sim/Process.py
rename : src/python/m5/objects/Root.py => src/sim/Root.py
rename : src/python/m5/objects/System.py => src/sim/System.py
extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-27 19:21:17 -07:00
Renamed from src/python/m5/objects/Device.py (Browse further)