Commit graph

3890 commits

Author SHA1 Message Date
Gabe Black 1344fc2668 ARM: Decode the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black e157b1f52a ARM: Implement the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 1884ed65bd ARM: Decode MRS and MSR for thumb. 2010-06-02 12:58:05 -05:00
Gabe Black ff3b21bc2b ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. 2010-06-02 12:58:05 -05:00
Gabe Black f0811eb208 ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black f61bb9adb9 ARM: Hook up the push/pop versions of stm/ldm in thumb. 2010-06-02 12:58:05 -05:00
Gabe Black a76ab8e040 ARM: Hook SVC into the thumb decoder. 2010-06-02 12:58:05 -05:00
Gabe Black cbdebf852e ARM: Implement SVC (was SWI) outside of the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black 34032f97d6 ARM: Trigger system calls from the SupervisorCall invoke method.
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
2010-06-02 12:58:05 -05:00
Gabe Black 52460938cb ARM: Fix multiply operations.
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
2010-06-02 12:58:05 -05:00
Gabe Black 4fb6fcd82d ARM: Decode the scalar saturating add/subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 30dd622622 ARM: Decode the parallel add and subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 62e8487d57 ARM: Implement signed saturating add and/or subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black a1253ec644 ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). 2010-06-02 12:58:05 -05:00
Gabe Black 61b00d3224 ARM: Decode unconditional ARM instructions. 2010-06-02 12:58:04 -05:00
Gabe Black b6e2f5d33f ARM: Make sure ldm exception return writes back its base in the right mode.
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
2010-06-02 12:58:04 -05:00
Gabe Black 89060f1fd8 ARM: Rework how unrecognized/unimplemented instructions are handled.
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
2010-06-02 12:58:04 -05:00
Gabe Black aa45fafb2e ARM: Add support for "SUBS PC, LR and related instructions". 2010-06-02 12:58:04 -05:00
Gabe Black 2419903dc0 ARM: Make ldrs into the PC and ldm exception return do interworking branches. 2010-06-02 12:58:04 -05:00
Gabe Black 28227440a7 ARM: Align the PC when using it as the base for a load. 2010-06-02 12:58:04 -05:00
Gabe Black d63f748b53 ARM: Implement ADR as separate from ADD. 2010-06-02 12:58:04 -05:00
Gabe Black e92dc21fde ARM: Add support for interworking branch ALU instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 11c3361be4 ARM: Fix when the flag bits are updated for thumb. 2010-06-02 12:58:04 -05:00
Gabe Black 14d25fbad0 ARM: Don't rely on undefined behavior to get arithmetic right shift.
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
2010-06-02 12:58:04 -05:00
Gabe Black 05d880f7a1 ARM: Restrict the shift amount from a register to 8 bits.
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
2010-06-02 12:58:04 -05:00
Gabe Black 9ebaf8ecd5 ARM: Define the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 3f83094af2 ARM: Decode the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 647edea970 ARM: Fix the constant describing the number of floating point registers. 2010-06-02 12:58:04 -05:00
Gabe Black 2f3102f1ef ARM: Add templates for VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 739f23c64c ARM: Add base classes for VFP load/store multiple. 2010-06-02 12:58:04 -05:00
Gabe Black cb631d87c3 ARM: Add floating point load/store microops. 2010-06-02 12:58:04 -05:00
Gabe Black 3a11412c99 ARM: Add an fp version of one of the microop indexed registers. 2010-06-02 12:58:04 -05:00
Gabe Black d5aee75efe ARM: Move the mmap region to where Linux actually has it. 2010-06-02 12:58:04 -05:00
Gabe Black a8eb9d521c ARM: Eliminate the unused rhi and rlo operands. 2010-06-02 12:58:03 -05:00
Gabe Black b02c7f1bcd ARM: Move the macro mem constructor out of the isa desc.
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
2010-06-02 12:58:03 -05:00
Gabe Black 7b62e9ad71 ARM: Make macroops panic if executed directly.
The macroop should never be executed, only it's microops will.
2010-06-02 12:58:03 -05:00
Ali Saidi 8fadf2691d ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs. 2010-06-02 12:58:03 -05:00
Gabe Black f18040a205 ARM: Split out the "basic" templates and format.
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
2010-06-02 12:58:03 -05:00
Gabe Black c175f1b993 ARM: Remove unnecessary cruft from includes.isa. 2010-06-02 12:58:03 -05:00
Gabe Black e29ec7d2ed ARM: Move the inst2string function out of the isa_desc.
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black ae135228fc ARM: Get rid of the unused ArmGenericCodeSubs. 2010-06-02 12:58:03 -05:00
Gabe Black 8c012e9571 ARM: Make the predecoder print out the ExtMachInst it gathered when traced. 2010-06-02 12:58:03 -05:00
Gabe Black 458bd025d4 ARM: Remove special naming for the new version of multiply. 2010-06-02 12:58:03 -05:00
Gabe Black 2196f75a25 ARM: Hook the new multiply instructions into all the decoders. 2010-06-02 12:58:03 -05:00
Gabe Black 33da368e99 ARM: Implement all integer multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 50229be27f ARM: Add templates for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 3430b34cff ARM: Add base classes for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black c7d2f43641 ARM: Decode plain binary immediate thumb data processing instructions. 2010-06-02 12:58:03 -05:00
Gabe Black dcf218155d ARM: Define a new "movt" data processing instruction. 2010-06-02 12:58:03 -05:00
Gabe Black b615ed1470 ARM: Hook the new branch instructions into the 32 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black 274badd201 ARM: Hook the new branch instructions into the 16 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black b6b2f8891a ARM: Eliminate the old style branch instructions. 2010-06-02 12:58:03 -05:00
Gabe Black d082705b01 ARM: Hook the new branch instructions into the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black 9869343636 ARM: Implement branch instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black a6c1c8debb ARM: Add new templates for branch instructions. 2010-06-02 12:58:02 -05:00
Gabe Black ef3972eaae ARM: Implement new base classes for branches. 2010-06-02 12:58:02 -05:00
Gabe Black 769f3406fe ARM: Replace the interworking branch base class with a special operand. 2010-06-02 12:58:02 -05:00
Gabe Black b6e7029dd5 ARM: Fix PC operand handling. 2010-06-02 12:58:02 -05:00
Gabe Black 7eb3ea2798 ARM: Remove the special naming from the new version of data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 4f08b52af2 ARM: Get rid of unnecessary flag calculating functions. 2010-06-02 12:58:02 -05:00
Gabe Black bf903ec9a1 ARM: Get rid of the unused Jump format. 2010-06-02 12:58:02 -05:00
Gabe Black 36ca0658a4 ARM: Get rid of obsoleted predicated inst formats, etc. 2010-06-02 12:58:02 -05:00
Gabe Black 7939b48265 ARM: Implement disassembly for the new data processing classes. 2010-06-02 12:58:02 -05:00
Gabe Black b66e3aec43 ARM: Hook the external data processing instructions into the Thumb decoder. 2010-06-02 12:58:02 -05:00
Gabe Black beb759912b ARM: Move the modified_imm function from all ARM instructions to just data processing ones. 2010-06-02 12:58:02 -05:00
Gabe Black 8136cb3605 ARM: Hook the new external data processing instructions to the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black bf45d44cbe ARM: Implement data processing instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black c02f9cdddf ARM: Add new base classes for data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 1e7b317a98 ARM: Hook up 32 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 64d6b6ebfd ARM: Hook up 16 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 51bde086d5 ARM: Reimplement load/store multiple external to the decoder.
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02 12:58:02 -05:00
Gabe Black 93a3714816 ARM: Move the templates for predicated instructions into a separate file.
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
2010-06-02 12:58:01 -05:00
Gabe Black 04300e33d4 ARM: Remove the special naming for the new memory instructions.
These are the only memory instructions now.
2010-06-02 12:58:01 -05:00
Gabe Black deb6e8f805 ARM: Eliminate the old memory formats which are no longer used. 2010-06-02 12:58:01 -05:00
Gabe Black 1905024766 ARM: Eliminate decoding for the very deprecated FPA instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 55465844dc ARM: Make the addressing mode 3 loads/stores use the externally defined instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
2010-06-02 12:58:01 -05:00
Gabe Black a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 462cf6f49b ARM: Make single stores decode to the new external store instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions.
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
2010-06-02 12:58:01 -05:00
Gabe Black fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b93015304 ARM: Define the store instructions from outside the decoder.
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02 12:58:01 -05:00
Gabe Black 81fdced83f ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder.
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
2010-06-02 12:58:01 -05:00
Gabe Black 4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 386424ccb5 ARM: Implement the 32 bit thumb load word instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 292b8a3c91 ARM: Add an operand for accessing the current PC. 2010-06-02 12:58:00 -05:00
Gabe Black 003346077f ARM: Flesh out 32 bit thumb load word decoding. 2010-06-02 12:58:00 -05:00
Gabe Black 0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. 2010-06-02 12:58:00 -05:00
Gabe Black af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. 2010-06-02 12:58:00 -05:00
Gabe Black 0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. 2010-06-02 12:58:00 -05:00
Gabe Black 659f8d021f ARM: Add bitfields for 32 bit thumb. 2010-06-02 12:58:00 -05:00
Gabe Black bc6ae010c9 ARM: Decode VFP instructions. 2010-06-02 12:58:00 -05:00