Commit graph

7958 commits

Author SHA1 Message Date
Korey Sewell
516b611462 inorder: define iterator for resource schedules
resource skeds are divided into two parts: front end (all insts) and back end (inst. specific)
each of those are implemented as separate lists,  so this iterator wraps around
the traditional list iterator so that an instruction can walk it's schedule but seamlessly
transfer from front end to back end when necessary
2011-02-12 10:14:43 -05:00
Korey Sewell
ec9b2ec251 inorder: stage scheduler for front/back end schedule creation
add a stage scheduler class to replace InstStage in pipeline_traits.cc
use that class to define a default front-end, resource schedule that all
instructions will follow. This will also replace the back end schedule in
pipeline_traits.cc. The reason for adding this is so that we can cache
instruction schedules in the future instead of calling the same function
over/over again as well as constantly dynamically alllocating memory on
every instruction to try to figure out it's schedule
2011-02-12 10:14:40 -05:00
Korey Sewell
6713dbfe08 inorder: cache instruction schedules
first step in a optimization to not dynamically allocate an instruction schedule
for every instruction but rather used cached schedules
2011-02-12 10:14:36 -05:00
Korey Sewell
af67631790 inorder: comments for resource sked class 2011-02-12 10:14:34 -05:00
Korey Sewell
800e93f358 inorder: remove unused file
inst_buffer file isn't used , so remove it
2011-02-12 10:14:32 -05:00
Korey Sewell
e65c15e931 inorder: remove unused isa ops
pass/fail ops were used for testing but arent part of isa
2011-02-12 10:14:26 -05:00
Ali Saidi
2055df8322 Stats: Update the statistics for vnc patch. 2011-02-11 18:29:36 -06:00
Ali Saidi
d4df9e763c VNC/ARM: Use VNC server and add support to boot into X11 2011-02-11 18:29:36 -06:00
Ali Saidi
d33c1d9592 VNC: Add VNC server to M5 2011-02-11 18:29:35 -06:00
Ali Saidi
ded4d319f2 Serialization: Allow serialization of stl lists 2011-02-11 18:29:35 -06:00
Giacomo Gabrielli
a05032f4df O3: Fix pipeline restart when a table walk completes in the fetch stage.
When a table walk is initiated by the fetch stage, the CPU can
potentially move to the idle state and never wake up.

The fetch stage must call cpu->wakeCPU() when a translation completes
(in finishTranslation()).
2011-02-11 18:29:35 -06:00
Giacomo Gabrielli
74eff1b71b O3: Fix a few bugs in the TableWalker object.
Uncacheable requests were set as such only in atomic mode.
currState->delayed is checked in place of currState->timing for resetting
currState in atomic mode.
2011-02-11 18:29:35 -06:00
Ali Saidi
1411cb0b0f SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.
This change fixes an issue where a DTLB fault occurs and redirects fetch to
handle the fault and the ITLB requires a walk which delays translation. In this
case the status of the cpu isn't updated appropriately, and an additional
instruction fetch occurs. Eventually this hits an assert as multiple instruction
fetches are occuring in the system and when the second one returns the
processor is in the wrong state.

Some asserts below are removed because it was always true (typo) and the state
after the initiateAcc() the processor could be in any valid state when a
d-side fault occurs.
2011-02-11 18:29:35 -06:00
Giacomo Gabrielli
e2507407b1 O3: Enhance data address translation by supporting hardware page table walkers.
Some ISAs (like ARM) relies on hardware page table walkers.  For those ISAs,
when a TLB miss occurs, initiateTranslation() can return with NoFault but with
the translation unfinished.

Instructions experiencing a delayed translation due to a hardware page table
walk are deferred until the translation completes and kept into the IQ.  In
order to keep track of them, the IQ has been augmented with a queue of the
outstanding delayed memory instructions.  When their translation completes,
instructions are re-executed (only their initiateAccess() was already
executed; their DTB translation is now skipped).  The IEW stage has been
modified to support such a 2-pass execution.
2011-02-11 18:29:35 -06:00
Ali Saidi
453dbc772d ARM: Fix timer calculations.
The timer calculations were a bit off so time would run faster than
it otherwise should
2011-02-11 18:29:35 -06:00
Ali Saidi
59bf0e7eb4 Timesync: Make sure timesync event is setup after curTick is unserialized
Setup initial timesync event in initState or loadState so that curTick has
been updated to the new value, otherwise the event is scheduled in the past.
2011-02-11 18:29:35 -06:00
Ali Saidi
b7457fc11e Ext: Add X11 keysym header files to ext directory. 2011-02-09 22:27:37 -06:00
Brad Beckmann
06dfee5cea ruby: removed duplicate make response call 2011-02-09 16:02:09 -08:00
Brad Beckmann
4eab18fd06 regess: protocol regression tester updates 2011-02-08 18:07:54 -08:00
Brad Beckmann
ea9d4c3a97 memtest: due to contention increase, increased deadlock threshold 2011-02-08 15:53:33 -08:00
Brad Beckmann
6ebd7c390b config: fixed minor bug connecting dma devices to ruby 2011-02-08 15:52:44 -08:00
Nilay Vaish
488280e48b MESI CMP: Unset TBE pointer in L2 cache controller
The TBE pointer in the MESI CMP implementation was not being set to NULL
when the TBE is deallocated. This resulted in segmentation fault on testing
the protocol when the ProtocolTrace was switched on.
2011-02-08 07:47:02 -06:00
Gabe Black
0851580aad Stats: Re update stats. 2011-02-07 19:23:13 -08:00
Gabe Black
1b64bfa933 Stats: Back out broken update. 2011-02-07 19:23:11 -08:00
Tim Harris
44e5e7e053 X86: Obey the wp bit of CR0.
If cr0.wp ("write protect" bit) is clear then do not generate page faults when
writing to write-protected pages in kernel mode.
2011-02-07 15:18:52 -08:00
Tim Harris
6da83b8a1b X86: Use all 64 bits of the lstar register in the SYSCALL_64 macroop.
During SYSCALL_64, use dataSize=8 when handling new rip (ref
http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit
address)
2011-02-07 15:16:27 -08:00
Tim Harris
2ea1aa8a4f X86: Fix JMP_FAR_I to unpack a far pointer correctly.
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.
2011-02-07 15:12:59 -08:00
Tim Harris
5810ab121c X86: Read the LDT/GDT at CPL0 when executing an iret.
During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).
2011-02-07 15:05:28 -08:00
Nilay Vaish
10b4b364d9 Orion: Replace printf() with fatal()
The code for Orion 2.0 makes use of printf() at several places where there as
an error in configuration of the model. These have been replaced with fatal().
2011-02-07 12:42:23 -06:00
Korey Sewell
1b4e788407 ruby: add stdio header in SRAM.hh
missing header file caused RUBY_FS to not compile
2011-02-07 12:19:46 -05:00
Gabe Black
2107258d24 X86: Add stats for the new x86 fs regressions. 2011-02-07 01:23:16 -08:00
Gabe Black
dd53743797 X86: Add scripts to support X86 FS configurations in the regressions. 2011-02-07 01:23:02 -08:00
Gabe Black
f8fc0419c5 X86, Config: Move the setting of work count options to a separate function.
This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.
2011-02-07 01:22:15 -08:00
Gabe Black
0c4b816d84 X86: Fix compiling vtophys.cc 2011-02-07 01:21:21 -08:00
Brad Beckmann
45f881919f regress: Regression Tester output updates 2011-02-06 22:14:23 -08:00
Brad Beckmann
f5aa75fdc5 ruby: support to stallAndWait the mandatory queue
By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).

--HG--
rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06 22:14:19 -08:00
Brad Beckmann
194a137498 ruby: minor fix to deadlock panic message 2011-02-06 22:14:19 -08:00
Brad Beckmann
3a388aff69 boot: script that creates a checkpoint after Linux boot up 2011-02-06 22:14:19 -08:00
Joel Hestness
ebe563e531 garnet: Split network power in ruby.stats
Split out dynamic and static power numbers for printing to ruby.stats
2011-02-06 22:14:19 -08:00
Brad Beckmann
5c2f4937b3 MOESI_hammer: fixed dir bug counting received acks 2011-02-06 22:14:19 -08:00
Brad Beckmann
7edab47448 ruby: numa bit fix for sparse memory 2011-02-06 22:14:19 -08:00
Tushar Krishna
4fa690e8ff MOESI_CMP_token: removed unused message fields 2011-02-06 22:14:19 -08:00
Brad Beckmann
273e3d4924 mem: Added support for Null data packet
The packet now identifies whether static or dynamic data has been allocated and
is used by Ruby to determine whehter to copy the data pointer into the ruby
request.  Subsequently, Ruby can be told not to update phys memory when
receiving packets.
2011-02-06 22:14:19 -08:00
Brad Beckmann
dfa8cbeb06 m5: added work completed monitoring support 2011-02-06 22:14:19 -08:00
Brad Beckmann
c41fc138e7 dev: fixed bugs to extend interrupt capability beyond 15 cores 2011-02-06 22:14:18 -08:00
Joel Hestness
3a2d2223e1 x86: Timing support for pagetable walker
Move page table walker state to its own object type, and make the
walker instantiate state for each outstanding walk. By storing the
states in a queue, the walker is able to handle multiple outstanding
timing requests. Note that functional walks use separate state
elements.
2011-02-06 22:14:18 -08:00
Joel Hestness
52b6119228 TimingSimpleCPU: split data sender state fix
In sendSplitData, keep a pointer to the senderState that may be updated after
the call to handle*Packet. This way, if the receiver updates the packet
senderState, it can still be accessed in sendSplitData.
2011-02-06 22:14:18 -08:00
Brad Beckmann
2da54d1285 ruby: Fix RubyPort to properly handle retrys 2011-02-06 22:14:18 -08:00
Joel Hestness
dedb4fbf05 Ruby: Fix to return cache block size to CPU for split data transfers 2011-02-06 22:14:18 -08:00
Joel Hestness
82844618fd Ruby: Add support for locked memory accesses in X86_FS 2011-02-06 22:14:18 -08:00