Commit graph

315 commits

Author SHA1 Message Date
Brad Beckmann 12daaed84a ruby: Added clock to ruby system
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann ed81489954 ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system.  Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects.  This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann 42bebab779 ruby: connects sm queues to the network 2010-01-29 20:29:18 -08:00
Steve Reinhardt a8ea70dac6 ruby: Calculate system total memory capacity in Python
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt 0b54f1db8e ruby: Add support for generating topologies in Python. 2010-01-29 20:29:17 -08:00
Steve Reinhardt 98c94cfe3c ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Gabe Black 93d89b288f X86: Record the memory mode when building an X86 system. 2009-12-19 01:49:34 -08:00
Brad Beckmann c6182199c5 m5: improvements to the ruby_fs.py file 2009-11-18 16:34:32 -08:00
Brad Beckmann 70a261c0ae m5: Added option to take a checkpoint at the end of simulation 2009-11-18 13:55:58 -08:00
Brad Beckmann b8c413e993 m5: Moved profile option since Simulation depends on it. 2009-11-18 13:55:58 -08:00
Brad Beckmann 90d6e2652f ruby: included ruby config parameter ports per core
Slightly improved the major hack need to correctly assign the number of ports
per core.  CPUs have two ports: icache + dcache.  MemTester has one port.
2009-11-18 13:55:58 -08:00
Brad Beckmann 3cf24f9716 ruby: Support for merging ALPHA_FS and ruby
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers.  Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Brad Beckmann c3204421d8 ruby: Ruby memtest python script. 2009-11-18 13:55:57 -08:00
Brad Beckmann 912f3d7074 removed libruby file reference from ruby_se.py 2009-10-16 08:15:53 -07:00
Nathan Binkert 9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Korey Sewell 6499174115 inorder-configs: update se.py
fix bug with  'numThreads=len(workloads)' which was counting characters of command-line not counting threads as intended.
Update numThreads for inorder/o3 cases and default to 1 for all other cases.
2009-09-16 09:46:26 -04:00
Korey Sewell 7858a8e68f configs: add maxinsts option on command line
-option to allow threads to run to a max_inst_any_thread which is more useful/quicker in a lot of
cases then always having to figure out what tick to run your simulation to.
2009-09-16 09:45:30 -04:00
Steve Reinhardt 15bb248013 Add an I/O cache to FS config even if there's just an "L2" cache. 2009-09-14 21:19:40 -07:00
Korey Sewell 6c46313556 se-configs: edit se.py to account for non-O3CPU workloads 2009-07-26 00:13:35 -04:00
Korey Sewell 44f80e7ca5 o3-smt: enforce numThreads parameter for SMT SE mode 2009-07-25 00:50:27 -04:00
Daniel Sanchez 93f2f69657 ruby: Working M5 interface and updated Ruby interface.
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11 10:38:46 -07:00
Korey Sewell c70241810d cpus: fix cpu progress event
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:51:31 -04:00
Gabe Black 8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Steve Reinhardt 6629d9b2bc mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Steve Reinhardt 97b6947eb7 Minor tweaks for future Ruby compatibility. 2009-04-21 08:17:36 -07:00
Gabe Black b8333a5155 X86: Actually put the PCI INTA entry into the MP tables. 2009-04-19 04:15:18 -07:00
Gabe Black 25e223c30f X86: Make E820 report nice, round (and correct) numbers. 2009-04-19 04:14:48 -07:00
Gabe Black 06d25dcd26 X86: Automatically make the IO APIC in an N CPU system have id N+1. 2009-04-19 02:39:19 -07:00
Steve Reinhardt 9b66e82897 configs: Allow M5_CPU2000 env var to set CPU2K binary path.
It would be nice to have a more comprehensive mechanism
but this is a big improvement over manually editing the script.
2009-04-15 12:52:31 -07:00
Gabe Black eafdf00eb3 X86: Add IRQ4 to the Intel MP tables. 2009-02-25 10:19:06 -08:00
Korey Sewell cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Gabe Black 1c5b9773bd X86: Find the natural lpj for this configuration. 2009-02-01 00:29:07 -08:00
Gabe Black a5ed1590bd X86: Add a root device to the kernel command line. 2009-02-01 00:27:49 -08:00
Gabe Black 70cd5bfce5 X86: Configure the first PCI interrupt. 2009-02-01 00:26:10 -08:00
Gabe Black 18f6c18323 X86: Hook in a hard drive image. 2009-02-01 00:24:26 -08:00
Gabe Black 01679bb416 X86: Take out the IDE noprobe kernel arguments. 2009-02-01 00:20:44 -08:00
Gabe Black bb7ad80bbe X86: Plug in an IDE controller. 2009-02-01 00:00:03 -08:00
Gabe Black d08b8e2b82 X86: Add some interrupt info to the intel MP tables. 2009-01-31 23:43:09 -08:00
Ali Saidi f4291aac25 Errors: Print a URL with a hash of the format string to find more information about an error. 2009-01-30 20:04:15 -05:00
Gabe Black 7b7a92d3f4 X86: Prevent Linux for probing for non-existant IDE controllers. 2009-01-25 20:36:24 -08:00
Gabe Black ff29e00112 X86: Add entries for the IO APIC to the MP table. 2008-10-11 16:12:34 -07:00
Gabe Black 526933e5d0 X86: Add an Intel MP table to the simulation. 2008-10-11 15:14:37 -07:00
Gabe Black 3af428606a X86: Rename the PC device to Pc.
--HG--
rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
2008-10-11 02:23:40 -07:00
Gabe Black ec0fb05d64 X86: Turn SMBios structures into simobjects. 2008-10-10 03:50:51 -07:00
Gabe Black b4dab225fd X86: Split makeLinuxX86System into makeLinuxX86System and makeX86System. 2008-10-10 03:50:30 -07:00
Ali Saidi 3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Michael Adler 5f42bfcd56 process: separate stderr from stdout
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout.  The
new default maintains stdout and stderr going to the host.  Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
2008-07-23 14:41:34 -07:00
Nathan Binkert 00df9016fe Rename SimConsole to Terminal since it makes more sense
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
2008-06-17 20:29:06 -07:00
Ali Saidi 7e6728450f Scripts: Check for the appropriate build type as soon as possible. 2008-06-13 01:09:06 -04:00
Gabe Black bceaa257a3 X86: Make the e820 table manually or automatically configurable from python. 2008-06-12 00:58:36 -04:00