1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
--HG--
extra : convert_revision : 8d905e1b297ae664d60f8c8ba48b2aac25437fc6
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.
configs/example/fs.py:
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
--HG--
extra : convert_revision : 078e22800ff83f6e950bf5cc6fb16a98320e7c51
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
--HG--
extra : convert_revision : 55737d3d10742a1913a376d1febbc5809f2fab8f
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
--HG--
extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
--HG--
extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
--HG--
extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
--HG--
extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such
src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such
--HG--
extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
--HG--
extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
--HG--
extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
--HG--
extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
