Gene WU
4d8f4db8d1
ARM: Use fewer micro-ops for register update loads if possible.
...
Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
2010-08-25 19:10:42 -05:00
Gabe Black
54a919f225
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
2010-08-25 19:10:42 -05:00
Gabe Black
6368edb281
ARM: Implement all ARM SIMD instructions.
2010-08-25 19:10:42 -05:00
Min Kyu Jeong
e6a0be648e
ARM: Improve printing of uop disassembly.
2010-08-23 11:18:42 -05:00
Gabe Black
e50e6a260f
ARM: Add a comment to vfp.cc that explains the asm statements.
2010-06-02 12:58:18 -05:00
Gabe Black
fcee2b3f31
ARM: Add comments to the classes in macromem.hh.
2010-06-02 12:58:18 -05:00
Gabe Black
362b747fdc
ARM: Move code from vfp.hh to vfp.cc.
2010-06-02 12:58:18 -05:00
Ali Saidi
35e35fc825
ARM: Make some of the trace code more compact
2010-06-02 12:58:18 -05:00
Gabe Black
0abec53564
ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.
2010-06-02 12:58:18 -05:00
Gabe Black
b6c2548a27
ARM: Get rid of the binary dumping function in utility.hh.
2010-06-02 12:58:17 -05:00
Gabe Black
f8d2ed708b
ARM: Get rid of the empty branch.cc.
2010-06-02 12:58:17 -05:00
Gabe Black
0c574987c8
ARM: Mark some ARM static inst functions as inline.
2010-06-02 12:58:17 -05:00
Gabe Black
358fdc2a40
ARM: Decode to specialized conditional/unconditional versions of instructions.
...
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
2010-06-02 12:58:17 -05:00
Gabe Black
e9c8f68c0f
ARM: Make undefined instructions obey predication.
2010-06-02 12:58:16 -05:00
Ali Saidi
b8ec214553
ARM: Implement ARM CPU interrupts
2010-06-02 12:58:16 -05:00
Gabe Black
237c0617a0
ARM: Implement conversion to/from half precision.
2010-06-02 12:58:16 -05:00
Gabe Black
04e196f422
ARM: Clean up VFP
2010-06-02 12:58:16 -05:00
Gabe Black
0fe0390f73
ARM: Clean up the implementation of the VFP instructions.
2010-06-02 12:58:16 -05:00
Gabe Black
c919ab5b4f
ARM: Fix double precision load/store multiple decrement.
...
When decrementing, the higher addressed half of a double word is at a 4 byte
smaller displacement.
2010-06-02 12:58:15 -05:00
Gabe Black
23ba9c7b96
ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.
2010-06-02 12:58:15 -05:00
Gabe Black
347ab6c704
ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after.
2010-06-02 12:58:15 -05:00
Gabe Black
fd82a47b96
ARM: Implement flush to zero for destinations as well.
2010-06-02 12:58:15 -05:00
Gabe Black
186273e5f3
ARM: Fix up nans to match ARM's expected behavior.
2010-06-02 12:58:15 -05:00
Gabe Black
8466999aef
ARM: Implement flush to zero mode for VFP, and clean up some corner cases.
2010-06-02 12:58:15 -05:00
Gabe Black
efbceff96a
ARM: Add barriers that make sure FP operations happen where they're supposed to.
2010-06-02 12:58:15 -05:00
Gabe Black
aa05e5401c
ARM: Implement the floating/fixed point VCVT instructions.
2010-06-02 12:58:15 -05:00
Gabe Black
86a1093992
ARM: Add code to extract and record VFP exceptions.
2010-06-02 12:58:14 -05:00
Gabe Black
c1f7bf7f0e
ARM: Add support for VFP vector mode.
2010-06-02 12:58:14 -05:00
Gabe Black
f245f4937b
ARM: Introduce new VFP base classes that are optionally microops.
2010-06-02 12:58:14 -05:00
Gabe Black
65f5204325
ARM: Implement the VFP version of vmul.
2010-06-02 12:58:14 -05:00
Gabe Black
1fcd389fa3
ARM: Make sure macroops aren't interrupted midinstruction.
...
Do this by setting the delayed commit flag for all but the last microop.
2010-06-02 12:58:12 -05:00
Gabe Black
67766cbf17
ARM: Fix the implementation of the VFP ldm and stm macroops.
...
There were four bugs in these instructions. First, the loaded value was being
stored into a floating point register as floating point, changing the value as
it was transfered. Second, the meaning of the "up" bit had been reversed.
Third, the statically sized microop array wasn't bit enough for all possible
inputs. It's now dynamically sized and should always be big enough. Fourth,
the offset was stored as an unsigned 8 bit value. Negative offsets would look
like moderately large positive offsets.
2010-06-02 12:58:12 -05:00
Gabe Black
1f059541d6
ARM: Add a new RegImmOp base class.
2010-06-02 12:58:12 -05:00
Gabe Black
6976b4890a
ARM: Add a RegRegImmOp base class.
2010-06-02 12:58:12 -05:00
Gabe Black
186cfe3ae3
ARM: Widen the immediate fields in the misc instruction classes.
2010-06-02 12:58:12 -05:00
Gabe Black
b87ebf382f
ARM: Add a function to decode VFP modified immediate constants.
2010-06-02 12:58:12 -05:00
Gabe Black
7eb4d02dd9
ARM: Add a function to decode SIMD modified immediate constants.
2010-06-02 12:58:12 -05:00
Gabe Black
5943f0fc84
ARM: Ignore writing a bad mode to CPSR with MSR.
2010-06-02 12:58:11 -05:00
Gabe Black
bb6fea91da
ARM: Implement the SRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
dbee6e0c54
ARM: Add a base class for SRS.
2010-06-02 12:58:11 -05:00
Gabe Black
a5ea52bb45
ARM: Allow flattening into any mode.
2010-06-02 12:58:11 -05:00
Gabe Black
fb23297914
ARM: Make a base class for instructions that use only an immediate.
2010-06-02 12:58:10 -05:00
Gabe Black
54ab07e636
ARM: Implement the strex instructions.
2010-06-02 12:58:10 -05:00
Gabe Black
faf6c727f6
ARM: Respect the E bit of the CPSR when doing loads and stores.
2010-06-02 12:58:10 -05:00
Gabe Black
1d5233958a
ARM: Implement the V7 version of alignment checking.
2010-06-02 12:58:10 -05:00
Gabe Black
ec4cd00b11
ARM: Add a base class for the RFE instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
3caa75d53a
ARM: Squash the low order bits of the PC when performing a regular branch.
2010-06-02 12:58:10 -05:00
Gabe Black
eb0823c4f2
ARM: Fix the implementation of BX to work in thumbEE mode.
2010-06-02 12:58:09 -05:00
Gabe Black
9d4a1bf2ba
ARM: Explicitly keep track of the second destination for double loads/stores.
2010-06-02 12:58:09 -05:00
Gabe Black
6c1b10043f
ARM: Rename the RevOp base class to something more generic.
2010-06-02 12:58:08 -05:00
