Commit graph

10 commits

Author SHA1 Message Date
Nathan Binkert
39a055645f includes: sort all includes 2011-04-15 10:44:06 -07:00
Matt Horsnell
031f396c71 ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops:

URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack
sp = sp + offset;         // optionally auto-increment
PC = URa; CPSR = URb;     // write to the PC and CPSR.

Importantly:
- writing to PC is handled in the last micro-op.
- loading occurs prior to state changes.
2011-03-17 19:20:19 -05:00
Gabe Black
63464d950e ARM: Seperate out the renamable bits in the FPSCR. 2010-08-25 19:10:42 -05:00
Gabe Black
a5ea52bb45 ARM: Allow flattening into any mode. 2010-06-02 12:58:11 -05:00
Gabe Black
a8eb9d521c ARM: Eliminate the unused rhi and rlo operands. 2010-06-02 12:58:03 -05:00
Gabe Black
4779020e13 ARM: Fix the integer register indexes.
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Gabe Black
8a4af3668d ARM: Support forcing load/store multiple to use user registers. 2009-11-08 15:49:03 -08:00
Gabe Black
48525f581c ARM: Split the condition codes out of the CPSR.
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
78bd8fe44f ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. 2009-11-08 01:59:20 -08:00
Gabe Black
4a454c4f47 ARM: Set up an intregs.hh for ARM.
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
2009-11-08 00:07:35 -08:00