Commit graph

283 commits

Author SHA1 Message Date
Ali Saidi
a1e8225975 ARM: Add checkpointing support 2010-11-08 13:58:25 -06:00
Ali Saidi
0f2bbe15dd ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is
counterproductive.
2010-11-08 13:58:24 -06:00
Ali Saidi
ea1167dd9f Bus: Have the I/O devices that return address ranges print them out.
This way we actually get device names associated with the devices.
2010-11-08 13:58:24 -06:00
Ali Saidi
0ea794bcf4 sim: Use forward declarations for ports.
Virtual ports need TLB data which means anything touching a file in the arch
directory rebuilds any file that includes system.hh which in everything.
2010-11-08 13:58:22 -06:00
Gabe Black
968447db66 MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha. 2010-10-17 23:15:53 -07:00
Gabe Black
9268f895d5 UART: Make the 8250's MCR return a deterministic value.
This change makes the 8250 device return the value it has for the MCR when
read instead of leaving the packet data unmodified/uninitialized. The value
the UART has for the MCR may not be right, but that's a seperate issue that
apparently hasn't caused any problems to date.
2010-10-09 12:41:31 -07:00
Ali Saidi
f0c0b8a7f6 ARM: Add a fake flash controller so that unmodified linux can boot
With this change an unmodified Linux kernel can boot in M5.
2010-10-01 16:04:02 -05:00
Prakash Ramrakhyani
9792bbc324 ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte
accesses which could set/clear different numbers of interrupts.
2010-10-01 16:04:00 -05:00
Steve Reinhardt
3f9f4bf3d6 devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore.  Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
2010-09-16 20:24:05 -07:00
Nathan Binkert
afafaf1dcb style: fix sorting of includes and whitespace in some files 2010-09-10 14:58:04 -07:00
Gene Wu
4b9de42439 Devices: Allow a device to specify that a request is uncachable. 2010-08-23 11:18:41 -05:00
Ali Saidi
c0ca01ec36 ARM: Change how the AMBA device ID checking is done to make it more generic 2010-08-23 11:18:40 -05:00
Ali Saidi
8ed4f0a02c ARM: Add I/O devices for booting linux
--HG--
rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py
rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc
rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh
2010-08-23 11:18:40 -05:00
Brad Beckmann
283be34a99 devices: Fixed periodic interrupts to work with draining
Added drain functions to the RTC and 8254 timer so that periodic interrupts
stop when the system is draining.  This patch is needed to checkpoint in
timing mode.  Otherwise under certain situations, the event queue will never
be completely empty.
2010-08-20 11:46:13 -07:00
Steve Reinhardt
0685ae7a2d bus: clean up default responder code.
Clean up some minor things left over from the default responder
change in rev 9af6fb59752f.  Mostly renaming the 'responder_set'
param to 'use_default_range' to actually reflect what it does...
old name wasn't that descriptive in the first place, but now
it really doesn't make sense at all.

Also got rid of the bogus obsolete assignment to 'bus.responder'
which used to be a parameter but now is interpreted as an
implicit child assignment, and which was giving me problems in
the config restructuring to come.  (A good argument for not
allowing implicit child assignments, IMO, but that's water under
the bridge, I'm afraid.)

Also moved the Bus constructor to the .cc file since that's
where it should have been all along.
2010-08-17 05:06:21 -07:00
Nathan Binkert
86a93fe7b9 stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
Steve Reinhardt
a529dbfe65 Act like enabling CPUs is no big deal,
rather than a scary thing that might not work.
2010-06-03 16:54:28 -07:00
Ali Saidi
f246be4cbc DMA: Make DmaPort generic enough to be used other places 2010-06-02 12:58:16 -05:00
Ali Saidi
322f345b51 ARM: Adjust some copyrights 2010-06-02 12:57:59 -05:00
Nathan Binkert
e99828b06a tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
Nathan Binkert
ebdd004eb2 uart: use integer versions of time instead of messing around with floats 2010-02-28 19:28:09 -08:00
Gabe Black
3e1cda5080 X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC. 2009-12-19 01:50:06 -08:00
Brad Beckmann
f54790977b m5: removed master and slave deletions.
The unresolved destructor call caused a seg fault when called.
2009-11-18 13:55:58 -08:00
Brad Beckmann
4d731a522d m5: fixed destructor to deschedule the tickEvent and event 2009-11-18 13:55:58 -08:00
Ali Saidi
1470dae8e9 ARM: Boilerplate full-system code.
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-17 18:02:08 -06:00
Nathan Binkert
2c5fe6f95e build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
Brad Beckmann
28204b2a96 fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread 2009-10-15 15:15:24 -07:00
Nathan Binkert
d9f39c8ce7 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
Nathan Binkert
9a8cb7db7e python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Gabe Black
f6bb7ec4eb RTC: Make calls to writeData update the RTCs internal representation of time. 2009-08-20 23:09:03 -07:00
Gabe Black
da3c3bfa98 X86: Make the real time clock actually keep track of time. 2009-08-20 00:42:43 -07:00
Gabe Black
bc67396ada X86: Don't insist on binary encoding for the RTC since we implement BCD. 2009-08-20 00:40:14 -07:00
Gabe Black
8f49cd1123 X86: Move the simulated date in X86_FS forward to 2012. 2009-08-17 20:25:15 -07:00
Gabe Black
38c2af17a5 X86: Set up the IDE device correctly, ie. with and using legacy ports. 2009-08-02 18:01:13 -07:00
Gabe Black
80aa771dbc IDE: Configure the IDE control to reflect the initial value of the command register. 2009-08-02 18:01:09 -07:00
Gabe Black
74584d79b6 MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
2009-07-21 01:09:05 -07:00
Nathan Binkert
7daed385bf typo: correct spelling 2009-07-02 16:48:22 -07:00
Nathan Binkert
a01437ab03 types: need typename keyword to get the type. 2009-06-05 11:40:02 -07:00
Nathan Binkert
6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Steve Reinhardt
b3d0a01eb3 igbe: Fix descriptor cache bug. 2009-05-20 21:52:32 -07:00
Nathan Binkert
8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert
eef3a2e142 types: Move stuff for global types into src/base/types.hh
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Gabe Black
06b3e3c303 X86: Implement lowest priority interrupts more correctly.
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
2009-04-26 02:09:54 -07:00
Gabe Black
2f34a7eaeb X86: Tell the function that sends int messages who to send to instead of figuring it out itself. 2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257 X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
2009-04-26 02:06:21 -07:00
Gabe Black
8d84f81e70 X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment. 2009-04-26 02:04:32 -07:00
Steve Reinhardt
e7fa4f2f8e i8254xGBe: major style overhaul.
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular indentation.
2009-04-22 01:58:53 -04:00
Steve Reinhardt
6629d9b2bc mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond.  Now there is just one on
the main memory bus.  The default bus responder on all other buses
is now the downstream cache's cpu_side port.  Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Gabe Black
e174239bd8 X86: Mask the PIC at startup to avoid a glitch which causes an NMI. 2009-04-19 04:15:06 -07:00