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1823 commits

Author SHA1 Message Date
Gabe Black
36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black
79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional. 
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
 2010-06-02 12:58:01 -05:00
Gabe Black
a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
462cf6f49b ARM: Make single stores decode to the new external store instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions. 
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
 2010-06-02 12:58:01 -05:00
Gabe Black
fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
3b93015304 ARM: Define the store instructions from outside the decoder. 
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
 2010-06-02 12:58:01 -05:00
Gabe Black
81fdced83f ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black
321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder. 
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
 2010-06-02 12:58:01 -05:00
Gabe Black
4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
386424ccb5 ARM: Implement the 32 bit thumb load word instructions. 2010-06-02 12:58:01 -05:00
Gabe Black
292b8a3c91 ARM: Add an operand for accessing the current PC. 2010-06-02 12:58:00 -05:00
Gabe Black
003346077f ARM: Flesh out 32 bit thumb load word decoding. 2010-06-02 12:58:00 -05:00
Gabe Black
0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black
bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. 2010-06-02 12:58:00 -05:00
Gabe Black
af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black
bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. 2010-06-02 12:58:00 -05:00
Gabe Black
0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black
cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. 2010-06-02 12:58:00 -05:00
Gabe Black
659f8d021f ARM: Add bitfields for 32 bit thumb. 2010-06-02 12:58:00 -05:00
Gabe Black
bc6ae010c9 ARM: Decode VFP instructions. 2010-06-02 12:58:00 -05:00
Gabe Black
7b8525287d ARM: Stub out the 16 bit thumb decoder. 2010-06-02 12:58:00 -05:00
Gabe Black
aaa619ea23 ARM: Add thumb bitfields to the ExtMachInst and the isa definition. 2010-06-02 12:58:00 -05:00
Gabe Black
a1838f2c79 ARM: Make the decoder handle thumb instructions separately. 
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
 2010-06-02 12:58:00 -05:00
Gabe Black
0dffd8ce79 ARM: Add a thumb bit bitfield. 2010-06-02 12:58:00 -05:00
Gabe Black
96be7e16c1 ARM: Make the predecoder handle Thumb instructions. 2010-06-02 12:58:00 -05:00
Gabe Black
f49cdb4f5d ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. 2010-06-02 12:58:00 -05:00
Gabe Black
330d9d4dbc ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. 2010-06-02 12:58:00 -05:00
Gabe Black
a59d219989 ARM: Add a bit to the ExtMachInst to select thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black
4ddeceba96 ARM: Allow ARM processes to start in Thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black
ebb273bb7b ARM: Add a new base class for instructions that can do an interworking branch. 2010-06-02 12:57:59 -05:00
Gabe Black
9ef82c0bc4 ARM: Track the current ISA mode using the PC. 2010-06-02 12:57:59 -05:00
Gabe Black
1c0d9806e5 ARM: Fix custom writer/reader code for non indexed operands. 2010-06-02 12:57:59 -05:00
Gabe Black
4b87bc887a ARM: Remove IsControl from operands that don't imply control transfers. 
Also remove IsInteger from CondCodes.
 2010-06-02 12:57:59 -05:00
Nathan Binkert
bb589d463b x86: put back code that I accidentally deleted 2010-05-25 20:15:44 -07:00
Nathan Binkert
13d64906c2 copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
Gabe Black
c5c559b6ab SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
Gabe Black
c4497dbf03 X86: Make the cvti2f microop sign extend its integer source correctly. 
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
 2010-05-12 00:51:35 -07:00
Gabe Black
cc76842f83 X86: Actual change that fixes div. How did that happen? 2010-05-12 00:49:12 -07:00
Gabe Black
2ee7a89209 X86: Update the base aux vector X86 processes install. 2010-05-03 00:44:08 -07:00
Gabe Black
7524fdda6a X86: Sometimes CPUID depends on ecx, so pass that in. 2010-05-02 00:40:17 -07:00
Gabe Black
51a3d65e25 X86: Finally fix a division corner case. 
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
 2010-05-02 00:39:29 -07:00
Nathan Binkert
e99828b06a tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
Steve Reinhardt
4d77ea7a57 cpu: fix exec tracing memory corruption bug 
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
 2010-03-23 08:50:57 -07:00
Nathan Binkert
1068ca85d0 scons: import ply to work around scons sys.path weirdness 2010-03-10 15:39:34 -08:00
Nathan Binkert
f0b4259e98 cpu_models: get rid of cpu_models.py and move the stuff into SCons 2010-02-26 18:14:48 -08:00
Nathan Binkert
ac106767c8 isa_parser: Make SCons import the isa_parser 
this is instead of forking a new interpreter
 2010-02-26 18:14:48 -08:00