Commit graph

9015 commits

Author SHA1 Message Date
Andreas Hansson
31b4ac5cec Config: Exit with fatal if a port is already connected
This patch turns the existing warning into a fatal, as there should
never be any cases where a (non-vector) port is assigned to and then
later connected to something else. If this behaviour is allowed, as it
used to be, there are cases where the wrong number of C++ ports are
created when instantiating objects with VectorPorts (obviously that
could be fixed, but the better approach is to simply not allow it).
2012-05-23 09:01:56 -04:00
Nilay Vaish
0bff8eb210 X86 Regression: update stats due to cc register split 2012-05-22 11:38:04 -05:00
Nilay Vaish
1031fe7b6f Ruby: Remove the unused src/mem/ruby/common/Driver.* files. 2012-05-22 11:35:58 -05:00
Nilay Vaish
6a966d5eeb Ruby Sequencer: Schedule deadlock check event at correct time
The scheduling of the deadlock check event was being done incorrectly as the
clock was not being multiplied, so as to convert the time into ticks. This
patch removes that bug.
2012-05-22 11:32:57 -05:00
Nilay Vaish
4d4d212ae9 X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
2012-05-22 11:29:53 -05:00
Marc Orr
16a559c9c6 x86 ISA: Implement the sse3 haddps instruction.
Shuffle the 32 bit values into position, and then add in parallel.
2012-05-19 04:32:25 -07:00
Gabe Black
250c40799d Syscalls: warn when the length argument to mmap is excessive.
If the length argument to mmap is larger than the arbitrary but reasonable
limit of 4GB, there's a good chance that the value is nonsense and not
intentional. Rather than attempting to satisfy the mmap anyway, this change
makes gem5 warn to make it more apparent what's going wrong.
2012-05-19 04:13:47 -07:00
Lena Olson
8fe8efeb34 Mem: Fix size check when allocating physical memory 2012-05-14 20:31:33 -05:00
Andreas Hansson
7f14ea0c00 Config: Fix a typo in the se.py script for setting fastmem
This patch changes a hardcoded index 0 to the appropriate CPU index so
that fastmem is set correctly for all the CPUs in the system.
2012-05-16 12:37:08 -04:00
Ali Saidi
e62beaaa8f ARM: update stats for clock frequency fix. 2012-05-10 18:04:29 -05:00
Koan-Sin Tan
0b2d5e20d1 ARM: fix the calculation of the values in the RV clocks
This clock is used by the linux scheduler.
2012-05-10 18:04:28 -05:00
Ali Saidi
331696582f stats: fix compilation of unit test. 2012-05-10 18:04:28 -05:00
Ali Saidi
ec50c78f83 stats: fix bug in assert for 2d vector 2012-05-10 18:04:28 -05:00
Chander Sudanthi
1965a89873 ARM: pl011 raw interrupt fix
Raw interrupt was not being set when interrupt was disabled.
This patch sets the raw interrupt regardless of the mask.
2012-05-10 18:04:28 -05:00
Chander Sudanthi
200689c53f ARM: EMM board address range fix
0x40000000 is reservered for external AXI addresses.  This address
range is not used currently.  Removed the range from the bridge.
2012-05-10 18:04:28 -05:00
Uri Wiener
29a5e6ff35 DOT: improved dot-based system visualization
Revised system visualization to reflect structure and memory hierarchy.
Improved visualization: less congested and cluttered; more colorful.
Nodes reflect components; directed edges reflect dirctional relation, from
a master port to a slave port. Requires pydot.
2012-05-10 18:04:27 -05:00
Uri Wiener
cb1b63ea61 DOT: fixed broken code for visualizing configuration using dot
Fixed broken code which visualizes the system configuration by generating a
tree from each component's children, starting from root.
Requires DOT (hence pydot).
2012-05-10 18:04:27 -05:00
Dam Sunwoo
f2f7fa1a1c ARM: guard masked symbol tables by default
Symbol tables masked with the loadAddrMask create redundant entries
that could conflict with kernel function events that rely on the
original addresses.  This patch guards the creation of those masked
symbol tables by default, with an option to enable them when needed
(for early-stage kernel debugging, etc.)
2012-05-10 18:04:27 -05:00
Ali Saidi
041b932428 mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
Ali Saidi
c02dc07424 Cache: restructure code that actually isn't a loop 2012-05-10 18:04:27 -05:00
Ali Saidi
e029941bda dev: use correct delete operation in SimpleDisk 2012-05-10 18:04:27 -05:00
Ali Saidi
d9b484b41a ARM: Fix incorrect use of not operators in arm devices 2012-05-10 18:04:27 -05:00
Ali Saidi
5745665509 gem5: assert before indexing intro arrays to verify bounds 2012-05-10 18:04:27 -05:00
Ali Saidi
4f66bcdd2e gem5: fix some iterator use and erase bugs 2012-05-10 18:04:27 -05:00
Ali Saidi
5ecaf30219 gem5: fix a number of use after free issues 2012-05-10 18:04:27 -05:00
Ali Saidi
da10fbf5ca base: fix a invalid ?: operator 2012-05-10 18:04:27 -05:00
Ali Saidi
8cee4dacc8 gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
Ali Saidi
798403b689 ARM: Update m5op assembly for thumb compilation. 2012-05-10 18:04:26 -05:00
Ali Saidi
413ba1fdaf stats: track if the stats have been enabled and prevent requesting master id
Track the point in the initialization where statistics have been registered.
After this point registering new masterIds can no longer work as some
SimObjects may have sized stats vectors based on the previous value. If someone
tries to register a masterId after this point the simulator executes fatal().
2012-05-10 18:04:26 -05:00
Ali Saidi
f6895e8bd4 Cache: Panic if you attempt to create a checkpoint with a cache in the system 2012-05-10 18:04:26 -05:00
Pritha Ghoshal
dc456d8166 IGbE: Fix writeback conditions for i8254x GbE in updated data sheet.
An older revision of the data sheet specified that txdctl.gran was 1 the granularity was
based on cache block and gran being 0 is based on descriptor count. The newer version of
the data sheet reverses this errata
2012-05-10 18:04:26 -05:00
Nathan Binkert
4a644767c5 stats: update stats for no_value -> nan
Lots of accumulated older changes too.
2012-05-09 11:52:14 -07:00
Nathan Binkert
55411f7f71 stats: use nan instead of no_value 2012-05-09 11:51:42 -07:00
Andreas Hansson
ab23e29487 MEM: Add the communication monitor
This patch adds a communication monitor MemObject that can be inserted
between a master and slave port to provide a range of statistics about
the communication passing through it. The communication monitor is
non-invasive and does not change any properties or timing of the
packets, with the exception of adding a sender state to be able to
track latency. The statistics are only collected in timing mode (not
atomic) to avoid slowing down any fast forwarding.

An example of the statistics captured by the monitor are: read/write
burst lengths, bandwidth, request-response latency, outstanding
transactions, inter transaction time, transaction count, and address
distribution. The monitor can be used in combination with periodic
resetting and dumping of stats (through schedStatEvent) to study the
behaviour over time.

In future patches, a selection of convenience scripts will be added to
aid in visualising the statistics collected by the monitor.
2012-05-09 04:37:45 -04:00
Steve Reinhardt
18e8d7ed2d scons: allow override of SWIG binary on command line 2012-05-08 07:49:57 -07:00
Andreas Hansson
692351ea34 MEM: Do not forward uncacheable to bus snoopers
This patch adds a guarding if-statement to avoid forwarding
uncacheable requests (or rather their corresponding request packets)
to bus snoopers. These packets should never have any effect on the
caches, and thus there is no need to forward them to the snoopers.
2012-05-08 05:15:52 -04:00
Andreas Hansson
15e28c5ba6 Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
This patch fixes a bug that caused snoop requests to be placed in a
packet queue. Instead, the packet is now sent immediately using
sendTimingSnoopReq, thus bypassing the packet queue and any normal
responses waiting to be sent.
2012-05-04 03:30:02 -04:00
Nilay Vaish
e8f56bdf45 Regression: Move x86 fs ruby simulation from quick to long
--HG--
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
2012-05-03 23:18:13 -05:00
Jayneel Gandhi
39cbae9581 Config: Fix help msg for option --mem-size 2012-05-03 05:17:29 -05:00
Andreas Hansson
3fea59e162 MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 13:40:42 -04:00
Nilay Vaish
8966e6d36d Regression: Stats update for X86 Ruby FS test
The kernel originally used to generate the stats is different from the one
at use on zizzer. This patch updates the stats with the correct kernel in
use.
2012-04-30 03:47:22 -05:00
Gabe Black
2c85cf41a2 X86: Fix the IMUL_R_P_I macroop.
The disp displacement was left off the load microop so the wrong value was
used.
2012-04-29 02:26:34 -07:00
Vince Weaver
03a91b0533 X86: Fix up the open system call's flags. 2012-04-29 00:31:03 -07:00
Vince Weaver
38799e2b3f X86: Make gem5 ignore a bunch of syscalls. 2012-04-29 00:30:56 -07:00
Nilay Vaish
04a558bb41 Garnet: Correct computation of link utilization
The computation for link utilization was incorrect for the flexible network.
The utilization was being divided twice by the total time.
2012-04-28 16:57:31 -05:00
Nilay Vaish
6ea7fcc54a util/regress: Add the missing comma in the list of builds 2012-04-26 20:28:45 -05:00
Nilay Vaish
86f248e2a7 Regression: Add a test for x86 timing full system ruby simulation 2012-04-25 22:43:36 -05:00
Nilay Vaish
c3dad222e3 Ruby: Remove extra statements from Sequencer 2012-04-25 17:52:03 -05:00
Andreas Hansson
beed20d7bc MEM: Use base class Master/SlavePort pointers in the bus
This patch makes some rather trivial simplifications to the bus in
that it changes the use of BusMasterPort and BusSlavePort pointers to
simply use MasterPort and SlavePort (iterators are also updated
accordingly).

This change is a step towards a future patch that introduces a
separation of the interface and the structural port itself.
2012-04-25 10:45:23 -04:00
Andreas Hansson
4c92708b48 MEM: Add the PortId type and a corresponding id field to Port
This patch introduces the PortId type, moves the definition of
INVALID_PORT_ID to the Port class, and also gives every port an id to
reflect the fact that each element in a vector port has an
identifier/index.

Previously the bus and Ruby testers (and potentially other users of
the vector ports) added the id field in their port subclasses, and now
this functionality is always present as it is moved to the base class.
2012-04-25 10:41:23 -04:00