a realworld file.
arch/alpha/isa_desc:
arch/alpha/pseudo_inst.hh:
implement the readfile pseudo instruction that will read a
chunk of a realworld file.
arch/alpha/pseudo_inst.cc:
implement the readfile pseudo instruction that will read a
chunk of a realworld file. The filename is a per system
parameter and comes from the system itself.
kern/linux/linux_system.cc:
sim/system.hh:
Create a per-system readfile parameter for use by the readfile
pseudo instruction. That way each system can get its own file.
--HG--
extra : convert_revision : 941b3a3e20702a6252b219ca66a6d90da2944c50
from the simulator into the simulatee
kern/tru64/dump_mbuf.cc:
rename CopyData -> CopyOut
--HG--
extra : convert_revision : e3ef27a5762dfc495dcb84a372470464c27557d2
arch/alpha/ev5.cc:
cpu/simple_cpu/simple_cpu.cc:
update for new event interface
base/stats/events.cc:
implement the ignore event function which matches sim objects from which
to ignore events.
Make insert event like insert data and make it able to insert many
events in a single transaction with the database.
base/stats/events.hh:
Make it possible to ignore events
sim/sim_object.cc:
make recordEvent a member function of SimObject to implement
the ignore function easily
sim/sim_object.hh:
implement the ignore event stuff in the sim object. This is a
bit of a hack, but an easy place to put it.
--HG--
extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.hh:
Ifdefed TLASER code
arch/alpha/vtophys.cc:
added back some code andrew removed and couldn't remember why.
--HG--
extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
Mostly a matter of keeping prefetches to invalid addrs
from messing up VM IPRs. Also discovered that wh64s were
not being treated as prefetches, when they really should be
(for the most part, anyway).
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
arch/alpha/ev5.cc:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
- Add Fault trace flag.
arch/alpha/isa_desc:
- Add NO_FAULT MemReq flag to indicate references that should not
cause page faults (i.e., prefetches).
- Mark wh64 as a "data prefetch" instruction so it gets controlled
properly by the FullCPU data prefetch control switch.
- Align wh64 EA in decoder so issue stage doesn't need to worry about it.
arch/alpha/isa_traits.hh:
- Get rid of intrlock flag for locking VM fault regs (a la EV5);
instead, just don't update regs on VPTE loads (a la EV6).
base/traceflags.py:
- Add Fault trace flag.
cpu/simple_cpu/simple_cpu.hh:
- Pass MemReq flags to writeHint() operation.
cpu/static_inst.hh:
Update comment re: prefetches.
--HG--
extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.
arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
Renamed OpClass enum members.
--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
base/stats/mysql.hh:
Rename of Statsistics namespace to stats... merge from head
--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
arch/alpha/ev5.cc:
Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future.
arch/isa_parser.py:
Added in FastCPU model.
--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
arch/alpha/ev5.cc:
Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
Merged in changes to remove CPU dependence.
arch/isa_parser.py:
Merged in changes.
cpu/static_inst.hh:
Includes FastCPU execute methods.
--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.
arch/alpha/alpha_memory.cc:
The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
Moved code that once existed within simpleCPU to ev5, and templatized it.
This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
Added declaration for execute() using FastCPUExecContext.
--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
arch/alpha/ev5.cc:
Add an event for faults
cpu/simple_cpu/simple_cpu.cc:
add events for uncached reads/writes
--HG--
extra : convert_revision : 747bdf12761e2de6ebbf54fecc9e0b71915b3a02
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set
arch/alpha/ev5.hh:
Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
Fix to work with real address translation
--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
instruction execute methods. Register i now means the instruction's
i'th src (or dest) operand, not architectural register i. Current
models that use the architectural reg index can look that up easily
in the instruction object. Future models that do register renaming
should find this much simpler to deal with.
arch/isa_parser.py:
Generate register accessors with an extra level of indirection.
cpu/simple_cpu/simple_cpu.hh:
Modify register accessors to use an extra level of indirection.
--HG--
extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
with an IsNonSpeculative flag.
No effect on results of non-full-system or SimpleCPU.
Very small impact on full-system FullCPU runs since old wrong-path
call_pal insts used to change the PC, where now they're treated
as no-ops.
arch/alpha/isa_desc:
Get rid of xc->misspeculating() checks, use IsNonSpeculative flag instead.
cpu/static_inst.hh:
Add IsNonSpeculative flag and isNonSpeculative() method to test it.
--HG--
extra : convert_revision : 7ec536bfc28b905c429c09eb920ed73ef2beeeba
out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
a pointer to an object that lives inside simulated memory.
Useful for doing a bit of analysis of what's going on in
the running kernel.
--HG--
extra : convert_revision : d78089cce5ec4334483a710ba512eaf18d9b0319
arch/alpha/isa_desc:
remove the annotation junk
Move some code to AlphaPseudo where it belongs
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
remove the annotation junk
add pseudo instruction code that was previously misplaced
--HG--
extra : convert_revision : 97db8402aa34e0bdf044b138c52331fc9e714986
switches. (Makes other uncommitted code easier to merge.)
arch/alpha/ev5.cc:
pass the address of both the old an new pcbb on context
switches
--HG--
extra : convert_revision : bff8c8d1b532ad5f9af6270169bbfb1b5c05256a
arch/alpha/alpha_memory.cc:
change to the main m5 tree convention for naming
base/traceflags.py:
add ide and pciconfigall traceflags
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kill some old binning styled stuff
--HG--
extra : convert_revision : 0558878906817975a714b1c7c08f9ee405468535
(Still not perfect though.)
arch/alpha/isa_desc:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file. Force all instruction
execution context into a single model-dependent class (SimpleCPU itself
for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
Do a better job of factoring out CPU model. (Still not perfect though.)
Pull execute() methods out of class declarations into separate section
of file, allowing (1) easier replication for different CPU models and
(2) a path to putting them all in a separate file.
Also restructure top level to allow parser to run under interactive
interpreter session for easier debugging.
cpu/exec_context.hh:
Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
StaticInst::execute no longer takes a CPU and an ExecContext,
just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
Add methods to redirect calls to ExecContext so SimpleCPU
can act as sole instruction execution context for itself.
Typedef SimpleCPU to SimpleCPUExecContext.
--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.
arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
Added ULL for 64bit ints
kern/linux/linux_system.cc:
Added a function to skip determine_cpu_caches, right now it is only used for
printing in proc, however in the future we may either want to implement the SC_CTL
IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
added event to skip determine_cpu_caches()
--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
arch/alpha/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
base/loader/symtab.cc:
base/loader/symtab.hh:
cpu/exetrace.cc:
Changed InstExec traces to always print a symbol name
dev/ide_ctrl.cc:
dev/ide_disk.cc:
Tabs
dev/ide_disk.hh:
Change buffer size
dev/tsunami_pchip.cc:
Fix translatePciToDma to support scatter gather mapping
kern/linux/linux_system.cc:
Force simulator to wait until remote debugger attaches (should be removed
or turned on/off with a flag)
--HG--
extra : convert_revision : 1d08aebe3f448c87a963dd613de3e2e0cff0d48d
Add support for generic visitors for stats and use them
to implement independent output functions.
Support for mysql output and some initial code for hacking
on mysql output with python
arch/alpha/pseudo_inst.cc:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/sat_counter.cc:
base/sat_counter.hh:
cpu/simple_cpu/simple_cpu.cc:
kern/tru64/tru64_events.cc:
sim/main.cc:
sim/process.cc:
sim/process.hh:
sim/sim_events.cc:
sim/sim_object.cc:
sim/system.hh:
update for changes in stats package
base/statistics.cc:
move the python output code to base/stats/puthon.(cc|hh)
and reimplement it as a visitor.
move the text output code to base/stats/text.(cc|hh) and
reimplement it as a visitor.
move the database stuff into base/stats/statdb.(cc|hh) and
get rid of the class. Put everything as globals in the
Statistics::Database namespace.
allocate unique ids for all stats.
directly implement the check routine and get rid of the
various dumping routines since they're now in separate files.
make sure that no two stats have the same name
clean up some loops
base/statistics.hh:
major changes to the statistics package again
lots of code was factored out of statistics.hh into several
separate files in base/stats/ (this will continue)
There are now two Stat package types Result and Counter that
are specified to allow the user to keep the counted type
separate from the result type. They are currently both doubles
but that's an experiment. There is no more per stat ability to
set the type. Statistics::Counter is not the same as Counter!
Implement a visitor for statistics output so that new output
types can be implemented independently from the stats package
itself.
Add a unique id to each stat so that it can be used to keep
track of stats more simply. This number can also be used in
debugging problems with stats.
Tweak the bucket size stuff a bit to make it work better.
fixed VectorDist size bug
cpu/memtest/memtest.cc:
Fix up for changes in stats package
Don't use value() since it doesn't work with binning. If you
want a number as a stat, and to use it in the program itself,
you really want two separate variables, one that's a stat,
and one that's not.
cpu/memtest/memtest.hh:
Fix up for changes in stats package
test/Makefile:
Try to build stuff now that directories matter
test/stattest.cc:
test all new output types
choose which one with command line options
--HG--
extra : convert_revision : e3a3f5f0828c67c0e2de415d936ad240adaddc89
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d
configuration unnecessarily awkward. Biggest changes are:
- External and internal object names now match in all cases. The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon. In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object. The latter sets of substitions
are:
s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;
- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file. Having it as a CPU proxy is
really awkward.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
Rename objects to match config name.
cpu/base_cpu.cc:
Uncomment SimObject define since SamplingCPU no longer
does this for us.
dev/ethertap.cc:
Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
Fix old SimObjectParam.
--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc
arch/alpha/isa_desc:
Need to return fault for copy operations.
cpu/exec_context.hh:
Add temporary storage to pass source address from copy load to copy store
cpu/simple_cpu/simple_cpu.cc:
Implement copy functions.
cpu/simple_cpu/simple_cpu.hh:
Return fault
--HG--
extra : convert_revision : 98e5ce563449d6057ba45c70eece9235f1649a90
arch/alpha/isa_desc:
Just to make sure, remove the new copy instructions until everything works.
--HG--
extra : convert_revision : cdd3d4c8fa415175aaee04f4a99340dcf82dbc3a
arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
arch/alpha/ev5.cc:
Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
(Very slightly).
arch/alpha/isa_desc:
Upper half of rpcc result comes from value written
to IPR_CC, not actual cycle counter.
--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
--HG--
extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
--HG--
extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
physical addressing. This has the uncacheable bit as bit 40 as opposed
to bit 39. Additionally, we now support (at least superficially) a 44-bit
physical address. To deal with superpage access in this scheme, any super
page access with either bit 39 or 40 set is sign extended.
--HG--
extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
tlb index calls that are called from ExecContext::readIpr
arch/alpha/ev5.cc:
Fix misspeculation bugs for misspeculated IPR accesses
--HG--
extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
Fix to remote debugger while in PAL code
dev/pcidev.cc:
Remove extra debug printf
--HG--
extra : convert_revision : e64988846ad05cd3ddf47034d72d99dae3501591
arch/alpha/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
--HG--
extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
benchmarks for alpha-linux.
arch/alpha/alpha_linux_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit, times and rt_sigaction.
Should eventually provide a function for times.
arch/alpha/alpha_tru64_process.cc:
Added some more ioctl commands to ignore.
Set unlink and rename to the new functions.
Ignore setrlimit.
sim/syscall_emul.cc:
Added implementations for unlink and rename.
sim/syscall_emul.hh:
Added unlink and rename functions.
Added a couple more ioctl requests to ignore.
Print out the PC of any ioctl commands that fail.
--HG--
extra : convert_revision : 8af21c7fa7d0645d3f9324c9ce70ad33590c3c8e
execution pipeline (Alpha trapb & excb).
Add support for write memory barriers (mostly impacts
store buffer).
Add StaticInst flag to indicate memory barriers, though
this is not modeled in the pipeline yet.
arch/alpha/isa_desc:
Implement trapb, excb, mb, and wmb as insts with
no execution effect (empty execute() function) but
with flags that indicate their side effects.
Also make sure every instruction that needs to go to
the execute stage has a real opClass value, since we
are now using No_OpClass to signal insts that can get
dropped at dispatch.
StaticInst::branchTarget() is now a const method.
cpu/static_inst.hh:
Add flags to indicate serializing insts (trapb, excb) and
memory and write barriers.
Also declare some StaticInst methods as const methods.
dev/etherlink.hh:
sim/eventq.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_object.hh:
Make name() return value const.
--HG--
extra : convert_revision : 39520e71469fa20e0a7446b2e06b494eec17a02c
arch/alpha/isa_desc:
Add missing branchTarget() method for indirect branches.
cpu/static_inst.hh:
Add comment clarifying when branchTarget() can be used
on indirect branches.
--HG--
extra : convert_revision : 0dcfb36a9792a338cefceb3d1501825abace7ac5
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
arch/alpha/isa_desc:
don't say warn: Warning:
base/misc.cc:
avoid printing two newlines in a row
sim/main.cc:
print out a message just before we enter the event queue
--HG--
extra : convert_revision : 2a824d4b67661903fc739a0fb0759aa91d72382c
arch/alpha/isa_traits.hh:
Add a constant for the maximum address value called MaxAddr.
--HG--
extra : convert_revision : 1371e8b713cc6ed134093e9c208db35dc9741ac7
Move global checkpoint-related functions and vars into Checkpoint class (as statics).
arch/alpha/pseudo_inst.cc:
dev/disk_image.cc:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
sim/serialize.cc:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
Checkpoint constructor now takes checkpoint directory name instead
of file name.
Make serialize:dir parameter actually set checkpoint directory name
instead of directory in which checkpoint directory is created. If
the value contains a '%', the curTick value is sprintf'd into the
format to create the directory name. The default is backwards compatible
with the old fixed name ("m5.%012d").
sim/serialize.hh:
Move global checkpoint-related functions and vars
into Checkpoint class (as statics).
Checkpoint constructor now takes checkpoint directory name instead
of file name.
--HG--
extra : convert_revision : d0aa87b62911f405a4f5811271b9e6351fdd9fe4
arch/alpha/alpha_tru64_process.cc:
So, I don't know why linux uses an off_t here.
I'm also not sure why linux defines an off_t to be a long
Let's just use long here since it works for linux, and that's
what bsd does
base/inifile.cc:
correct #include for OpenBSD
dev/disk_image.cc:
the correct type for this is streampos
--HG--
extra : convert_revision : f3ac3a3b8515d66e07ffb9780d8a9e387297b6a0
makefile, such that decoder.cc was not getting rebuilt.
Also add -fno-strict-aliasing to fix all the bizarre problems
I've been having with g++ 3.3.x.
arch/alpha/isa_desc:
Fix compilation problems. AlphaISA is a class now, not a namespace.
--HG--
extra : convert_revision : 1583cebc1258c57cbd286c1955d11648150fa1f4
arch/alpha/alpha_memory.cc:
Rename md_mode_type to mode_type.
arch/alpha/ev5.cc:
simPalCheck() only gets called on correct path now, so
there's no need to test misspeculating().
arch/alpha/isa_desc:
Get privileged call_pall detection right this time (I hope).
ExecContext::simPalCheck() and Annotate::Callpal() are now
called only on non-speculative executions... this should fix
the bogus pal-call stats we've been seeing (since these are
incremented in simPalCheck()).
Also check for invalid call_pall function codes.
--HG--
extra : convert_revision : 465d6724884007d3fa066d14cd5e6db0cd3954e1
a checkpoint now gives identical results to running from scratch
and doing at switchover at the same cycle!
- CPUs start at cycle 0 again, not cycle 1.
- curTick is now serialized & unserialized.
- Stats get reset in main (before event loop). Since this is done
after curTick is unserialized, simTicks gets set correctly for
running from a checkpoint.
- Simplify serialization to happen in a single pass.
- s/Serializeable/Serializable/
arch/alpha/isa_traits.hh:
dev/etherlink.hh:
sim/eventq.cc:
sim/eventq.hh:
s/Serializeable/Serializable/
kern/tru64/tru64_system.cc:
sim/process.cc:
Make initial CPU activation on cycle 0 again (not 1).
sim/main.cc:
Reset stats before getting started.
Make error message on falling out of event loop
more meaningful.
sim/serialize.cc:
sim/serialize.hh:
Get rid of now-useless initial pass; serialization is
done in a single pass now.
Serialize & unserialize curTick.
Wrap curTick and mainEventQueue in a "globals" Serializable object.
s/Serializeable/Serializable/
sim/sim_object.cc:
Add static function to serialize all SimObjects.
sim/sim_object.hh:
Add static function to serialize all SimObjects.
s/Serializeable/Serializable/
--HG--
extra : convert_revision : 9dcc411d0009b54b8eb61c3a509680b81b9f6f68
and SimpleCPU::setStatus() into separate functions. For example,
setStatus(Active) is now activate().
--HG--
extra : convert_revision : 4392e07caf6c918db0b535f613175109681686fe
interfaces, and specific support for Alpha Linux. Split syscall emulation
functions into several groups, based on whether they depend on the specific
OS and/or architecture (and all combinations of above), including the use of
template functions to support syscalls with slightly different constants
or interface structs.
arch/alpha/alpha_tru64_process.cc:
Incorporate full Tru64 object definition here, including structure and constant definitions.
This way we can wrap all of the functions inside the object, and not worry about namespace
conflicts because no one outside this file will ever see it.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
Add enums to ObjectFile to indicate the object's architecture and operating system.
cpu/exec_context.cc:
prog.hh is now process.hh
cpu/exec_context.hh:
prog.hh is now process.hh
move architecture-specific syscall arg accessors into ExecContext
cpu/simple_cpu/simple_cpu.cc:
No need to include prog.hh (which has been renamed)
sim/process.cc:
sim/process.hh:
LiveProcess is now effectively an abstract base class.
New LiveProcess::create() function takes an object file and dynamically picks the
appropriate subclass of LiveProcess to handle the syscall interface that file expects
(currently Tru64 or Linux).
--HG--
rename : arch/alpha/fake_syscall.cc => arch/alpha/alpha_tru64_process.cc
rename : sim/prog.cc => sim/process.cc
rename : sim/prog.hh => sim/process.hh
extra : convert_revision : 4a03ca7d94a34177cb672931f8aae83a6bad179a
arch/alpha/pseudo_inst.hh:
Give temporary access of these functions to full cpu junk
(this is a hack!)
--HG--
extra : convert_revision : 35499d6bf03b1c21dc918ccc09a6d21719262120
arch/alpha/fake_syscall.cc:
Fix a couple of bugs:
- error return codes weren't making it through due to inadvertent cast to unsigned
- sigreturn broken in not one but two ways
- make all file descriptors look like plain files (not ttys)
Added implementations of setuid, getgid, fcntl, and getdirentries from Dave Oehmke
--HG--
extra : convert_revision : 53d3f13e1b05e3bde9e68ada3774ca39fa4c0d4c
arch/alpha/isa_desc:
A few disassembly changes to make it easier to compare with old machine.def traces:
- Make lds prefetches print f31 instead of r31 as dest.
- Don't print mode suffixes on FP if SS_COMPATIBLE_DISASSEMBLY
cpu/exetrace.cc:
Left-justify instruction in field, and increase width by 1.
--HG--
extra : convert_revision : 9ffd56728f1bb772aa3ccda5f027b93d4c3a4135
arch/alpha/isa_desc:
move the quiesce instruction out of here so I can conditionally
enable it.
arch/alpha/pseudo_inst.cc:
conditionally enable quiesce
arch/alpha/pseudo_inst.hh:
add quiesce
--HG--
extra : convert_revision : e1c474c4bf8761ff58073785d82b2bec9f632885
arch/alpha/isa_desc:
Move the pseudo instructions out of the isa_desc, into their own
file and call out to them when they're to be accessed
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
move SimExit to sim_exit.cc
--HG--
extra : convert_revision : 1c393adb1c18bd0fef065057d7f4e9cf60ac4197
resetstats
dumpstats
dumpresetstats
m5checkpoint
Lots of cleanup of serialization and stats dumping/resetting to
work with these new instructions
arch/alpha/isa_desc:
Implement more m5 pseduo opcodes:
resetstats
dumpstats
dumpresetstats
m5checkpoint
All of these functions take two optional parameters, the first is a delay,
and the second is a period. The delay tells the simulator to wait the
specified number of nanoseconds before triggering the event, the period
tells the simulator to repeat the event with a specified frequency
base/statistics.cc:
base/statistics.hh:
regReset RegResetCallback
dev/disk_image.cc:
serializeFilename -> CheckpointFile()
sim/debug.cc:
Move this debugging statement to sim_stats.cc
sim/eventq.cc:
Don't AutoDelete an event if it is scheduled since the process()
function could potentially schedule the event again.
sim/main.cc:
DumpStatsEvent is now Statistics::SetupEvent(Dump, curTick)
sim/serialize.cc:
Change the serialize event so that it's possible to cause the
event to repeat. Also make the priority such that the event
happens just before the simulator would exit if both events
were scheduled for the same cycle.
get rid of the serializeFilename variable and provide a CheckpointFile()
function. This function takes a basename that is set in the
configuration, and appends the current cycle to the name so that
multiple checkpoints can be dumped from the same simulation.
Also, don't exit the simulation when a checkpoint file is dumped.
sim/serialize.hh:
serializeFilename -> CheckpointFile()
SetupCheckpoint function to tell the simulator to prepare
to checkpoint at a certain time with a certain period
sim/sim_events.cc:
DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
The context stuff gets moved into the already existing
stats context in stat_context.cc
sim/sim_events.hh:
DumpStatsEvent stuff gets move to sim_stats.(cc|hh)
sim/universe.cc:
Provide some simple functions for converting times into
ticks. These use floating point math to get as close as
possible to the real values. Multipliers are set up ahead
of time
--HG--
extra : convert_revision : d06ef26a9237529a1e5060cb1ac2dcc04d4ec252
Implement a new m5exit instruction with an optional delay
arch/alpha/isa_desc:
move m5exit to m5exit old. The old version of the
instruction is now deprecated
Implement the new exit instruction with the optional delay
sim/sim_events.cc:
sim/sim_events.hh:
Make SimExit take a cycle
sim/universe.cc:
provide ticksPerMS, ticksPerUS, and ticksPerNS so we don't
have to do math during the cycle
--HG--
extra : convert_revision : e2ed47a2e5cfcd57c82086c6fcb4a28bf801c214
Can now serialize & unserialize DmaRequestEvents and DmaTransferEvents.
Also support serialize/unserialize of pointers to SimObjects and
other Serializable objects.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Events get serialized by the event queue only if they're marked
as AutoSerialize... others are assumed to be serialized by something
else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
Define Checkpoint object to encapsulate everything you need to know
about a checkpoint. Use it to allow lookups of named Serializable
objects (and SimObjects) during unserialization.
unserialize() now takes a Checkpoint* instead of an IniFile*.
--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
Serialize TLB contents.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Complete serialization of SimpleCPU (including owned events).
sim/eventq.cc:
sim/eventq.hh:
Basic serialization for events.
Still need to handle dynamic events (not owned by a SimObject).
sim/serialize.cc:
sim/serialize.hh:
Export serialization filename so PhysicalMemory can
derive its filename from that.
--HG--
extra : convert_revision : 4db851c5880f73f576ca092d5e5ad4256048eb51
Add support for serializing enums.
arch/alpha/isa_traits.hh:
Add serialize/unserialize functions for RegFile
(defined in new isa_traits.cc).
cpu/exec_context.cc:
Flesh out serialize/unserialize.
sim/serialize.hh:
Add {UN}SERIALIZE_ENUM().
--HG--
extra : convert_revision : 9e30c7e7b3b290dc8ea0888ba3636fc93ee89052
though most objects don't actually serialize any data.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
Change unserialize param from IniFile& to const IniFile*.
cpu/simple_cpu/simple_cpu.cc:
Change unserialize param from IniFile& to const IniFile*.
Make unserialize call ExecContext::unserialize.
sim/eventq.cc:
Rename MainEventQueue (no spaces) for easier parsing in checkpoints.
Disable event serialization for now, so we can focus on the easy stuff.
sim/serialize.cc:
Change paramIn and arrayParamIn param from IniFile& to const IniFile*.
sim/serialize.hh:
Change unserialize, paramIn, and arrayParamIn params from IniFile& to const IniFile*.
--HG--
extra : convert_revision : 6e8853ed375eddec0e140c95a01dd51bd225f7b9
arch/alpha/ev5.cc:
Don't call kernelStats.hwrei() or system->breakpoint() on misspeculated paths.
arch/alpha/isa_desc:
Don't write reegs.intrflag, do Annotate::Callpal, or call xc->syscall
on misspeculated paths.
--HG--
extra : convert_revision : e73b96fbe4ac5be85fb20aa218fd05fd56d5b2f3
in the process make m5_exit more generic
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
There's no reason that this needs to be in an arch specific file
arch/alpha/isa_desc:
m5_exit -> SimExit
Emulate callpal halt and cause the simulator to exit
while we're at it, sort #includes
sim/sim_events.cc:
sim/sim_events.hh:
move the m5_exit function here, renaming it to SimExit.
Also Allow the caller to pass in the termination message.
--HG--
extra : convert_revision : 54b43b17a412ab387b8672c27ef0b04fce10ee15
