Commit graph

11799 commits

Author SHA1 Message Date
Radhika Jagtap
36bb848104 mem: Add instruction sequence number to request
This patch adds the instruction sequence number to the request and provides a
request constructor that accepts a sequence number for initialization.
2015-12-07 16:42:15 -06:00
Radhika Jagtap
de4dc50e95 proto, probe: Add elastic trace probe to o3 cpu
The elastic trace is a type of probe listener and listens to probe points
in multiple stages of the O3CPU. The notify method is called on a probe
point typically when an instruction successfully progresses through that
stage.

As different listener methods mapped to the different probe points execute,
relevant information about the instruction, e.g. timestamps and register
accesses, are captured and stored in temporary InstExecInfo class objects.
When the instruction progresses through the commit stage, the timing and the
dependency information about the instruction is finalised and encapsulated in
a struct called TraceInfo. TraceInfo objects are collected in a list instead
of writing them out to the trace file one a time. This is required as the
trace is processed in chunks to evaluate order dependencies and computational
delay in case an instruction does not have any register dependencies. By this
we achieve a simpler algorithm during replay because every record in the
trace can be hooked onto a record in its past. The instruction dependency
trace is written out as a protobuf format file. A second trace containing
fetch requests at absolute timestamps is written to a separate protobuf
format file.

If the instruction is not executed then it is not added to the trace.
The code checks if the instruction had a fault, if it predicated
false and thus previous register values were restored or if it was a
load/store that did not have a request (e.g. when the size of the
request is zero). In all these cases the instruction is set as
executed by the Execute stage and is picked up by the commit probe
listener. But a request is not issued and registers are not written.
So practically, skipping these should not hurt the dependency modelling.

If squashing results in squashing younger instructions, it may happen that
the squash probe discards the inst and removes it from the temporary
store but execute stage deals with the instruction in the next cycle which
results in the execute probe seeing this inst as 'new' inst. A sequence
number of the last processed trace record is used to trap these cases and
not add to the temporary store.

The elastic instruction trace and fetch request trace can be read in and
played back by the TraceCPU.
2015-12-07 16:42:15 -06:00
Radhika Jagtap
eb19fc2976 probe: Add probe in Fetch, IEW, Rename and Commit
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows.

A probe point is added in the Fetch stage for probing when a fetch request is
sent. Notify is fired on the probe point when a request is sent succesfully in
the first attempt as well as on a retry attempt.

Probe points are added in the IEW stage when an instruction begins to execute
and when execution is complete. This points can be used for monitoring the
execution time of an instruction.

Probe points are added in the Rename stage to probe renaming of source and
destination registers and when there is squashing. These probe points can be
used to track register dependencies and remove when there is squashing.

A probe point for squashing is added in Commit to probe squashed instructions.
2015-12-07 16:42:15 -06:00
Andreas Sandberg
bbcbe028fe stats: Update to reflect changes to PCI handling 2015-12-05 00:11:25 +00:00
Andreas Sandberg
78275c9d2f dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.
2015-12-05 00:11:24 +00:00
Pau Cabre
abfb997800 cpu: fix unitialized variable which may cause assertion failure
The assert in lsq_unit_impl.hh line 963 needs pktPending to be initialized to
NULL (I got the assertion failure several times without the fix).

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-12-04 17:54:03 -06:00
Bjoern A. Zeeb
e746231682 util: term: drop CC from Makefile
With clang there are systems without gcc being installed anymore and we should
not rely on that.  This patch drops CC so that system's default compiler is
invoked.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-12-04 17:25:45 -06:00
Abdul Mutaal Ahmad
0707f4ee63 util: DrainManager/Checkpoint changes in SystemC coupling
Due to changes in Drain Manager, the lastest systemc coupling doesn't work. The
code for handling Checkpoint has been modified and it is now compatiable with
new drain manager.

Testing is being done on systemC coupling. It needs more testing to verify
checkpointing feature.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-12-04 17:20:07 -06:00
Andreas Sandberg
1a34e23603 sim: Get rid of the non-const serialize() method
The last SimObject using the legacy serialize API with non-const
methods has now been transitioned to the new API. This changeset
removes the serializeOld() methods from the serialization base class
as they are no longer used.
2015-12-04 09:48:48 +00:00
Andreas Sandberg
5a249e03a4 stats: Update to reflect changes to RealView platform code 2015-12-04 00:19:05 +00:00
Andreas Sandberg
6a05179e13 arm, config: Automatically discover available platforms
Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
b3f7a62876 dev, arm: Disable R/B swap in HDLCD by default
The HDLCD model implements a workaround that swaps the red and blue
channels. This works around an issue in certain old kernels. The new
driver doesn't seem to have this behavior, so disable the workaround
by default and enable it in the affected platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
4aeaaf7985 dev, arm: Split MCC and DCC subsystems
Devices behind the Versatile Express configuration controllers are
currently all lumped into one SimObject. This will make DTB generation
challenging since the DTB assumes them to be in different parts of the
hierarchy. It also makes it hard to model other CoreTiles without also
replicating devices from the motherboard.

This changeset splits the VExpressCoreTileCtrl into two subsystems:
VExpressMCC for all motherboard-related devices and CoreTile2A15DCC
for Core Tile specific devices.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
daa53da594 sim: Add support for generating back traces on errors
Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
2015-12-04 00:12:58 +00:00
Andreas Sandberg
a1aeff27ce arm: Add support for automatic boot loader selection
Add support for automatically selecting a boot loader that matches the
guest system's kernel. Instead of accepting a single boot loader, the
ArmSystem class now accepts a vector of boot loaders. When
initializing a system, the we now look for the first boot loader with
an architecture that matches the kernel.

This changeset makes it possible to use the same system for both
64-bit and 32-bit kernels.
2015-12-03 23:53:37 +00:00
Andreas Sandberg
146dfd0356 dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the
class name) to the TsunamiPChip. If someone decides to implement PCI
for Malta, they should make sure to share code with the Tsunami
implementation if they are similar.
2015-12-03 23:09:34 +00:00
Andreas Hansson
00b2bd7437 stats: Bump stats to match current behaviour 2015-12-02 09:58:24 -05:00
Andreas Sandberg
c84745e2cb config: Fix broken SimObject listing
The gem5 option '--list-sim-objects' is supposed to list all available
SimObjects and their parameters. It currently chokes on SimObjects
with parameters that have an object instance as their default
value. This is caused by __str__ in SimObject trying to resolve its
complete path. When the path resolution method reaches the parent
object (a MetaSimObject since it hasn't been instantiated), it dies
with a Python exception.

This changeset adds a guard to stop path resolution if the parent
object is a MetaSimObject.
2015-12-01 13:01:05 +00:00
Andreas Sandberg
d7e3d94c14 dev: Remove unnecessary header include
--HG--
extra : rebase_source : 64046371962e98413757bc3ab0c0d48dfb11ff1e
2015-11-24 10:13:04 +00:00
Andreas Hansson
72b14f7ef6 mem: Fix search-replace issues in DRAMPower wrapper license
Fix a number of unintentional insertions of 'const'.
2015-11-25 13:52:56 -05:00
Andrew Bardsley
4375678a0d config: Added missing types to JSON/INI Python reader
Added the missing types EthernetAddr and Current to the JSON/INI file
reader example configs/example/read_config.py.

Also added __str__ to EthernetAddr to make values appear in the same form
in JSON an INI files.
2015-11-22 05:10:21 -05:00
Andrew Bardsley
4596a33e10 sim: Update C++ config example to match SystemC example
Update the use of the drain manager, and checkpointing to
match changes to gem5 since the example was written.
2015-09-10 16:10:49 +01:00
Geoffrey Blake
1e1cd2dc01 arm, dev: Fix flash model serialization code typos
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint.  This patch fixes these typos.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
488128dab2 cpu: Fix base FP and CC register index in o3 insertThread()
Note that the method is not used, and could possibly be deleted.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
bbdd7cecb9 arm: Fix fplib 128-bit shift operators
Appease clang.
2015-11-22 05:10:18 -05:00
Andreas Hansson
6adb728fb4 config: Minor fixes to the DRAM utilisation sweep 2015-11-22 05:10:17 -05:00
Andreas Hansson
949437d559 cpu: Fix memory leak in traffic generator
In cases where we discard the packet, make sure to also delete it and
the associated request.
2015-11-22 05:10:16 -05:00
Andreas Sandberg
d57a855e40 cpu: Enforce 1 interrupt controller per thread
Consider it a fatal configuration error if the number of interrupt
controllers doesn't match the number of threads in an SMT
configuration.
2015-11-20 14:50:17 -06:00
Nilay Vaish
90d430d5b3 Merged changesets: 47e2adf7fb1a and b65d4e878ed2
--HG--
extra : amend_source : c51de9ae5387aba6fae8403677054678beceb2ab
2015-11-16 05:10:45 -06:00
Nilay Vaish
de489e1997 stats: updates due to recent chagnesets 2015-11-16 05:08:57 -06:00
Swapnil Haria
08cec03f8e x86: Invalidating TLB entry on page fault
As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel.  This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11
2015-11-16 05:08:54 -06:00
Bjoern A. Zeeb
f50e92d2c7 x86: cpuid: add family to warn() message
doCpuid() has to identical warn messages about unimplemented functions.  Add
the family to the log message to make them distinguishable.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Bjoern A. Zeeb
5c49635f20 x86: pagetable walker: fix typo in comment 2015-11-16 04:58:39 -06:00
Palle Lyckegaard
a95e8ab887 sparc: Make remote debugging with gdb work
Remove sparc V8 TBR register from list of registers since it is not part of
sparc V9. This brings the number of registers in sync with what gdb expects

Without this patch gdb complains about receoved packet too long.

with this patch gdb is able to work properly with gem5 for remote debugging.

Note: gdb is version 7.8
Note: gdb is configured with --target=sparc64-sun-solaris2.8

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Nilay Vaish
e1385784f2 stats: remove wb_penalized and wb_penalized_rate 2015-11-16 04:58:29 -06:00
Nilay Vaish
1d268a1f2d o3: drop unused statistic wbPenalized and wbPenalizedRate 2015-11-16 04:57:52 -06:00
Joe Gross
fe9cf5100a sim: support for distcc pump server settings 2015-11-15 17:56:43 -05:00
Andreas Sandberg
2a6fe97092 arm: Add missing explicit overrides for classic caches
Make clang when compiling on OSX.
2015-11-15 21:28:00 +00:00
Brad Beckmann
95f20a2905 ruby: added stl vector of ints to be used by SLICC 2015-07-20 09:15:20 -05:00
Tony Gutierrez
d10fac27bc slicc: fixes for the Address to Addr changeset (11025)
misc changes now that Address has become Addr including int to address util
function
2015-11-13 17:30:58 -05:00
Joe Gross
5143d480f3 ruby: add BoolVec
The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool
2015-11-13 17:30:56 -05:00
Brad Beckmann
aef8d851bd mem: add boolean to disable PacketQueue's size sanity check
the sanity check, while generally useful for exposing memory system bugs,
may be spurious with respect to GPU workloads, which may generate many more
requests than typical CPU workloads. the large number of requests generated
by the GPU may cause the req/resp queues to back up, thus queueing more than
100 packets.
2015-07-20 09:15:18 -05:00
Anthony Gutierrez
7678ddeb46 misc: ignore object files and static libs in util/m5 2015-11-13 17:03:48 -05:00
Andreas Sandberg
0ee18f5b66 dev, arm: Initialized the iccrpr register in the GIC
The IICRPR register in the GIC is currently not being initialized when
the GIC is instantiated. Initialize to the value mandated by the
architecture specification.
2015-11-11 10:18:38 +00:00
Sascha Bischoff
9d23e6d323 dev: Add basic checkpoint support to VirtIO9PProxy device
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
2015-11-05 09:40:12 +00:00
Andreas Sandberg
9719b261a1 dev: Remove unused header includes
Devices should never need to include dev/pciconfall.hh.

--HG--
extra : amend_source : 3a6e56485d432b49e2af22407982fa785c0ccb68
2015-11-09 13:44:15 +00:00
Andreas Sandberg
c62fe43ba9 dev: Don't access the platform directly in PCI devices
Cleanup PCI devices to avoid using the PciDevice::platform pointer
directly. The PCI-specific functionality provided by the Platform
should be accessed through the wrappers in PciDevice.
2015-11-09 13:44:04 +00:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Andreas Hansson
337774e192 config: Update memtest to stress test clean writebacks
This patch adds yet another twist to the memtest cache hierarchy, in that
the writeback_clean option is toggled at every level to match the
clusivity of the downstream cache.
2015-11-06 03:26:44 -05:00
Andreas Hansson
7433d77fcf mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.

The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.

The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py
2015-11-06 03:26:43 -05:00