make fp writes also chatty with the Sparc traceflag
src/arch/sparc/floatregfile.cc:
make fp writes also chatty with the Sparc traceflag
src/cpu/exetrace.cc:
fix comparing fp registers between legion and m5
--HG--
extra : convert_revision : f3703afae56249f137451262bc1b6919d465e714
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
--HG--
extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct
src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232
pretty close to compiling w/ suns compiler
briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops
SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa:
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start on the first part of it when we come back
--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc:
make AsiIsLittle() be all the little asis.
Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
clean up the do*Fault code.... Make it work like legion, in particular
pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
implement some more twin ASIs
src/arch/sparc/tlb.cc:
All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
softint is supported now, no more need to
--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)
--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0
--HG--
extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
src/arch/sparc/interrupts.hh:
condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
implement HINTP
src/arch/sparc/ua2005.cc:
don't post interrupt unless it is enabled.
--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
fix for lookup table to keep it consistant with tlb on a replace of a specific entry
--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
Increment instruction count on first micro-op instead of last
src/arch/sparc/isa/decoder.isa:
Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
Add IsFirstMicroop flag to static insts
--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge between ali and me.
--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
formatting/indentation for case statements
src/arch/sparc/ua2005.cc:
formatting/indentation for case statements
--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
src/arch/sparc/ua2005.cc:
i SWEAR i committed this already, but apparently i didnt. ust start using HPSTATE::hpriv, etc. to access bitfields.
--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
src/arch/sparc/intregfile.cc:
some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
legion always returns du and dl set, so we need to emulate that for now at least
--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis
src/arch/sparc/miscregfile.cc:
get rid of some warnings
fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
make warning less verbose
--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile
src/arch/alpha/interrupts.hh:
small fix for alpha compile
src/arch/alpha/pagetable.hh:
small fix so ALPHA_FS will build on macs
--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
src/arch/sparc/interrupts.hh:
fill in how we do interrupts on sparc a little bit.
1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
2) fill in getInterrupts() a little bit.
also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
1) update formatting
2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.
--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
src/arch/sparc/faults.cc:
1) s/Resumeable/Resumable/gc
2) s/if(/if (/gc
3) keep variables lowercase
4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
add bitfield masks for some important ASRs (HPSTATE, PSTATE).
--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.cc:
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
correct protection defines
src/arch/sparc/ua2005.cc:
set the softint appropriately on an timer compare interrupt
--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
turn warnings into dprintfs
src/arch/sparc/miscregfile.cc:
turn dprintfn into dprintfs
--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
InstObjParam interface.
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
Add (read|write)MiscRegOperand calls to Alpha DynInst.
--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
Hand Merge
--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed
To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.
Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.
--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
--HG--
extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
