Commit graph

891 commits

Author SHA1 Message Date
Lisa Hsu
0fa30e579e Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-13 14:33:59 -05:00
Lisa Hsu
a983c4968c Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-13 14:33:32 -05:00
Lisa Hsu
5d42fd836b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12 21:19:51 -05:00
Kevin Lim
bc05f5982e Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12 17:55:50 -05:00
Kevin Lim
c7ad7b44eb Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly.  The eon benchmark should run now.

src/cpu/o3/iew_impl.hh:
    Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).

--HG--
extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
2006-12-12 17:35:46 -05:00
Steve Reinhardt
6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-12 09:58:40 -08:00
Steve Reinhardt
cdc3e5bc22 Get rid of unused lock code.
--HG--
extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
2006-12-12 02:21:03 -05:00
Kevin Lim
34924ce3b8 Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
2006-12-11 23:51:21 -05:00
Kevin Lim
1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-11 23:47:30 -05:00
Steve Reinhardt
cfc6710f63 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
2006-12-09 22:05:30 -08:00
Ali Saidi
4947bf276e fix lisa's hand merge
--HG--
extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-09 18:27:54 -05:00
Ali Saidi
2eef266c45 Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
2006-12-09 18:00:49 -05:00
Ali Saidi
81a00fdcfe Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data

src/arch/sparc/faults.cc:
    Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
    allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
    fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
    cleanup/fix page table code
src/arch/sparc/tlb.cc:
    implement more mmaped iprs, fix numbered insertion  code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
    add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
    dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.

--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
2006-12-09 18:00:40 -05:00
Lisa Hsu
369e10d95a Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge

--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08 15:07:26 -05:00
Lisa Hsu
da6c1f5b09 mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
    add in thread_context.hh to get access to tc.
    get rid of stubs that don't make sense right now.
    implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
    softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
    add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
    implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.

--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-08 14:37:31 -05:00
Ali Saidi
ed22eb781d get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07 18:50:33 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
2006-12-06 14:23:31 -05:00
Steve Reinhardt
1c28682cea Don't compress data on writebacks unless it's actually necessary.
--HG--
extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
2006-12-05 07:16:36 -08:00
Ali Saidi
4d57cab49a forgot to commit miscreg file
--HG--
extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
2006-12-04 20:29:55 -05:00
Gabe Black
8b1bcc3f52 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

--HG--
extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
2006-12-04 19:56:04 -05:00
Gabe Black
251f4e1134 Add in code to pass the ASI to translation.
--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
2006-12-04 19:55:52 -05:00
Ali Saidi
8e75b6e2a5 reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)
Protect other pieces of code so that sparc compiles SE again

src/arch/sparc/SConscript:
    Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
    add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
    wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
    reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
    protect legion code so it doesn't try to compile under se

--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
2006-12-04 19:39:57 -05:00
Ali Saidi
153e02a435 Legion actually writes to tl-1 in the data structure, so we need to compare correctly
--HG--
extra : convert_revision : 60fef1bd5dc03d7b107150dba922dd4a3f51626f
2006-12-04 18:22:55 -05:00
Steve Reinhardt
5fbf3aa471 Turn cache MissQueue/BlockingBuffer into virtual object
instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
2006-12-04 09:10:53 -08:00
Ali Saidi
92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-04 00:54:40 -05:00
Steve Reinhardt
7a1120ab20 Merge vm1.(none):/home/stever/bk/newmem-head
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 321f7fcc8bd6c6aaaab92d10172814f4d07d5e65
2006-12-02 22:26:40 -08:00
Steve Reinhardt
e6d7e8af21 Support better param conversions to/from numeric subclasses.
--HG--
extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
2006-12-02 22:24:52 -08:00
Steve Reinhardt
4c0014a187 Fix help strings on GenRepl params.
--HG--
extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
2006-12-02 22:23:46 -08:00
Steve Reinhardt
6f94c3c8d7 Make cache compression policy a runtime virtual thing
instead of a template policy.

--HG--
extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
2006-12-02 22:22:58 -08:00
Kevin Lim
c0f21b09c8 Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
    Fixes for MIPS_SE compile.

--HG--
extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
2006-12-02 13:33:46 -05:00
Ali Saidi
8c4f7a0404 Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
    We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
    Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
    Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
    Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
    fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
    Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
    Let kernel be none
src/sim/system.cc:
    Let the system kernel be none, but warn about it

--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-30 15:51:54 -05:00
Ali Saidi
7b9ef9716b Add TLB Dprintfs
fix addr alignment problem

--HG--
extra : convert_revision : c691611d4d32bc95d0ae30243b30cd6634e7772b
2006-11-29 20:32:43 -05:00
Gabe Black
36c03001bb Fixes to get compilation.
--HG--
extra : convert_revision : cd6b496c4e4b32ce2a639eb9a2b6fbd62dfff2d1
2006-11-29 17:59:42 -05:00
Gabe Black
5bdf4400b2 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29 17:34:20 -05:00
Ali Saidi
544f4b4d81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
2006-11-29 17:11:20 -05:00
Ali Saidi
b2eecd643c Add support for mmapped iprs to atomic cpu
src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
2006-11-29 17:11:10 -05:00
Kevin Lim
c96160cef5 Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created.  A flyspray task has been created for this issue.  It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.

src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated.  This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
    Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
    Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
    Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
    Instead of initializing the ports, simply connect them, deleting any old ports that might exist.  This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
    Ports are no longer initialized, but rather connected at context activation time.

--HG--
extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
2006-11-29 16:07:55 -05:00
Kevin Lim
4fb38e892f Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress

--HG--
extra : convert_revision : ffc7931d7da153b421b3c838a0968e484fd182ec
2006-11-28 11:41:17 -05:00
Kevin Lim
2b5fdf6033 Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting.
--HG--
extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
2006-11-28 11:41:08 -05:00
Steve Reinhardt
6bbb86dfa9 Add TRACING_ON setting for m5.prof.
--HG--
extra : convert_revision : ebda49bff30d76d3209acce55458d3f4e29594d3
2006-11-27 02:16:24 -05:00
Gabe Black
f2daf210f1 Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24 22:06:33 -05:00
Gabe Black
5f446e36b6 Merge zower:/eecshome/m5/newmem
into  ewok.(none):/home/gblack/m5/newmemo3

--HG--
extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
2006-11-24 14:08:44 -05:00
Gabe Black
d0f4a4c441 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
2006-11-24 14:08:43 -05:00
Gabe Black
c6ddab95df Rename this function.
--HG--
extra : convert_revision : 57ea1e1d3b75e35abb3310d392ec70086fff699a
2006-11-24 14:01:18 -05:00
Gabe Black
7708217167 Fix weird type modifier.
--HG--
extra : convert_revision : 7372b7a92b3c9d05388acb43ba58ada18464fa24
2006-11-24 14:00:45 -05:00
Gabe Black
96a6af98e2 Fix an include problem.
--HG--
extra : convert_revision : 89be55bd3f4f9b452a680a98b69ce42b80546769
2006-11-24 14:00:00 -05:00
Steve Reinhardt
28f8318252 Add no-op versions of ivlb and ivle back in for backwards compatibility.
--HG--
extra : convert_revision : 383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
2006-11-24 12:32:33 -05:00
Ali Saidi
6e9cf9411f Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
2006-11-23 01:44:49 -05:00