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Author SHA1 Message Date
Ali Saidi c2d5d2b53d ARM: Set the high bits in the part number so it's considered new by some code. 2010-08-25 19:10:42 -05:00
Ali Saidi 99fafb72b8 ARM: Fix VFP enabled checks for mem instructions 2010-08-25 19:10:42 -05:00
Gabe Black 63464d950e ARM: Seperate out the renamable bits in the FPSCR. 2010-08-25 19:10:42 -05:00
Gabe Black 93ce7238bf ARM: Eliminate some unused enums. 2010-08-25 19:10:42 -05:00
Gabe Black 0efe2f6769 ARM: Fix type comparison warnings in Neon. 2010-08-25 19:10:42 -05:00
Gabe Black 54a919f225 ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled. 2010-08-25 19:10:42 -05:00
Gabe Black 6368edb281 ARM: Implement all ARM SIMD instructions. 2010-08-25 19:10:42 -05:00
Gabe Black f4f6b31df1 ARM: Expand the mode checking utility functions. 
inUserMode now can take either a threadcontext or a CPSR value directly. If
given a thread context it just extracts the CPSR and calls the other version.
An inPrivelegedMode function was also implemented which just returns the
opposite of inUserMode.
 2010-08-25 19:10:41 -05:00
Gabe Black 943c171480 ISA: Get rid of old, unused utility functions cluttering up the ISAs. 2010-08-23 16:14:20 -07:00
Min Kyu Jeong e6a0be648e ARM: Improve printing of uop disassembly. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong d2fac84b95 ARM: Clean up flattening for SPSR adding 2010-08-23 11:18:41 -05:00
Gene Wu a02d82f9f8 ARM: Implement DBG instruction that doesn't do much for now. 2010-08-23 11:18:41 -05:00
Gene Wu d6736384b2 MEM: Make CLREX a first class request operation and clear locks in caches when it in received 2010-08-23 11:18:41 -05:00
Gene Wu 23626d99af ARM: Make sure that software prefetch instructions can't change the state of the TLB 2010-08-23 11:18:41 -05:00
Gene Wu 1fd104fc35 ARM: Don't write tracedata on writes, it might have been freed already. 2010-08-23 11:18:41 -05:00
Gene Wu 9db2ab8a62 ARM: Implement CLREX init/complete acc methods 2010-08-23 11:18:41 -05:00
Gene Wu f29e09746a ARM: Fix Uncachable TLB requests and decoding of xn bit 2010-08-23 11:18:41 -05:00
Gene Wu aa601750f8 ARM: For non-cachable accesses set the UNCACHABLE flag 2010-08-23 11:18:41 -05:00
Gene Wu 7405f4b774 ARM: Implement DSB, DMB, ISB 2010-08-23 11:18:41 -05:00
Gene Wu aabf478920 ARM: Get SCTLR TE bit from reset SCTLR 2010-08-23 11:18:41 -05:00
Gene Wu 1f032ad345 ARM: Implement CLREX 2010-08-23 11:18:41 -05:00
Gene Wu 66bcbec96e ARM: BX instruction can be contitional if last instruction in a IT block 
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong 92ae620be8 ARM: mark msr/mrs instructions as SerializeBefore/After 
Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong 5f91ec3f46 ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. 
THis allows the CPU to handle predicated-false instructions accordingly.
This particular patch makes loads that are predicated-false to be sent
straight to the commit stage directly, not waiting for return of the data
that was never requested since it was predicated-false.
 2010-08-23 11:18:40 -05:00
Min Kyu Jeong 7acf67971c ARM: adding genMachineCheckFault() stub for ARM that doesn't panic 2010-08-23 11:18:40 -05:00
Gene Wu 5486fa6612 ARM: DFSR status value for sync external data abort is expected to be 0x8 in ARMv7 2010-08-23 11:18:40 -05:00
Gene Wu a993188034 ARM: Temporary local variables can't conflict with isa parser operands. 
PC is an operand, so we can't have a temp called PC
 2010-08-23 11:18:40 -05:00
Ali Saidi 0c434b7f56 ARM: Exclusive accesses must be double word aligned 2010-08-23 11:18:40 -05:00
Ali Saidi 5148c693d8 ARM: Add some registers for big loads/stores to support neon. 2010-08-23 11:18:40 -05:00
Ali Saidi fc1730044e ARM: Decode neon memory instructions. 2010-08-23 11:18:40 -05:00
Gabe Black d1362d582a ARM: Clean up the ISA desc portion of the ARM memory instructions. 2010-08-23 11:18:40 -05:00
Ali Saidi 230acc291c ARM: We don't currently support ThumbEE exceptions, so don't report that we do 2010-08-23 11:18:40 -05:00
Ali Saidi bb5377899a ARM: Add system for ARM/Linux and bootstrapping 2010-08-23 11:18:40 -05:00
Ali Saidi 38cf6a164d ARM: Implement some more misc registers 2010-08-23 11:18:40 -05:00
Ali Saidi b7b2eae6fa ARM: Fix an un-initialized variable bug 2010-08-23 11:18:39 -05:00
Ali Saidi f2642e2055 Loader: Make the load address mask be a parameter of the system rather than a constant. 
This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
 2010-08-23 11:18:39 -05:00
Min Kyu Jeong d4e83a4001 ARM: Finish the timing translation when taking a fault. 2010-08-23 11:18:39 -05:00
Dam Sunwoo cb76111a7e ARM: Use a stl queue for the table walker state 2010-08-23 11:18:39 -05:00
Ali Saidi ac575a9d82 Compiler: Fixes for GCC 4.5. 2010-08-23 11:18:39 -05:00
Steve Reinhardt f064aa3060 sim: revamp unserialization procedure 
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
 2010-08-17 05:17:06 -07:00
Gabe Black 8cec870568 ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault. 2010-07-15 02:11:56 -07:00
Gabe Black 4e3183cb1e ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index. 2010-07-13 22:41:47 -07:00
Nathan Binkert 86a93fe7b9 stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
Ali Saidi d2186857b1 ARM: Fix issue with m5.fast and ARM 2010-06-03 12:20:49 -04:00
Ali Saidi 5268067f14 ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all 
Spec2k benchmarks seem to run with atomic or timing mode simple
CPUs. Fixed up some constants, handling of 64 bit arguments,
and marked a few more syscalls ignoreFunc.
 2010-06-02 12:58:18 -05:00
Min Kyu Jeong 5d5bf8cbc7 ARM: Fix IT state not updating when an instruction memory instruction faults. 2010-06-02 12:58:18 -05:00
Dam Sunwoo 4325519fc5 ARM: Allow multiple outstanding TLB walks to queue. 2010-06-02 12:58:18 -05:00
Ali Saidi 2bad5138e4 ARM TLB: Fix bug in memAttrs getting a bogus thread context 2010-06-02 12:58:18 -05:00
Dam Sunwoo 6b00c7fa22 ARM: Support table walks in timing mode. 2010-06-02 12:58:18 -05:00
Dam Sunwoo 6c8dd32fa4 ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...) 2010-06-02 12:58:18 -05:00
Gabe Black 85ba2a3243 ARM: Decode the neon instruction space. 2010-06-02 12:58:18 -05:00
Gabe Black e50e6a260f ARM: Add a comment to vfp.cc that explains the asm statements. 2010-06-02 12:58:18 -05:00
Gabe Black 10031a0327 ARM: Move some case values out of ##included files. 
This will help keep the high level decode together and not have it spread into
the subordinate decode stuff. The ##include lines still need to be on a line
by themselves, though.
 2010-06-02 12:58:18 -05:00
Gabe Black 22f15ab94e ARM: Combine some redundant cases in one of the data decode functions. 2010-06-02 12:58:18 -05:00
Gabe Black fcee2b3f31 ARM: Add comments to the classes in macromem.hh. 2010-06-02 12:58:18 -05:00
Gabe Black 362b747fdc ARM: Move code from vfp.hh to vfp.cc. 2010-06-02 12:58:18 -05:00
Ali Saidi 35e35fc825 ARM: Make some of the trace code more compact 2010-06-02 12:58:18 -05:00
Gabe Black 0abec53564 ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file. 2010-06-02 12:58:18 -05:00
Gabe Black 9223725973 ARM: Move the ISA "clear" function into isa.cc. 2010-06-02 12:58:17 -05:00
Gabe Black b6c2548a27 ARM: Get rid of the binary dumping function in utility.hh. 2010-06-02 12:58:17 -05:00
Gabe Black f8d2ed708b ARM: Get rid of the empty branch.cc. 2010-06-02 12:58:17 -05:00
Gabe Black 0c574987c8 ARM: Mark some ARM static inst functions as inline. 2010-06-02 12:58:17 -05:00
Gabe Black ba7a7b0394 ARM: Move some predecoder stuff into a .cc file. 
--HG--
rename : src/arch/arm/predecoder.hh => src/arch/arm/predecoder.cc
 2010-06-02 12:58:17 -05:00
Gabe Black 358fdc2a40 ARM: Decode to specialized conditional/unconditional versions of instructions. 
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
 2010-06-02 12:58:17 -05:00
Gabe Black 596cbe19d4 ARM: Make sure undefined unconditional ARM instructions decode as such. 2010-06-02 12:58:17 -05:00
Gabe Black 6101e1b062 ARM: Implement a version of mcr and mrc that works in user mode. 2010-06-02 12:58:17 -05:00
Gabe Black e91e6ff9a4 ARM: Hook the misc instructions into the thumb decoder. 2010-06-02 12:58:17 -05:00
Gabe Black 22d1a84509 ARM: Move some miscellaneous instructions out of the decoder to share with thumb. 2010-06-02 12:58:17 -05:00
Gabe Black 0e556e9dfb ARM: Treat LDRD in ARM with an odd index as an undefined instruction. 2010-06-02 12:58:17 -05:00
Ali Saidi 3dc6a8070e ARM: fix sizes of structs for ARM Linux 2010-06-02 12:58:17 -05:00
Ali Saidi d3a519ef0c ARM: Fixup native trace support and add some v7/recent stack code 2010-06-02 12:58:17 -05:00
Gabe Black 5a6bf8301a ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder. 2010-06-02 12:58:17 -05:00
Gabe Black 563db6cb99 ARM: Make sure the upc is zeroed when vectoring to a fault. 2010-06-02 12:58:17 -05:00
Ali Saidi 5d67be7b1e ARM: Implement the getrusage syscall. 2010-06-02 12:58:17 -05:00
Gabe Black 6e39288be0 ARM: Implement the bkpt instruction. 2010-06-02 12:58:16 -05:00
Gabe Black e9c8f68c0f ARM: Make undefined instructions obey predication. 2010-06-02 12:58:16 -05:00
Gabe Black 05bd3eb4ec ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR. 2010-06-02 12:58:16 -05:00
Gabe Black b93ceef538 ARM: Get rid of some of the old FP implementation. 2010-06-02 12:58:16 -05:00
Ali Saidi c1e1de8d69 ARM: Some TLB bug fixes. 2010-06-02 12:58:16 -05:00
Ali Saidi 7de7ea3b22 ARM: Move Miscreg functions out of isa.hh 2010-06-02 12:58:16 -05:00
Ali Saidi cb9936cfde ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. 2010-06-02 12:58:16 -05:00
Ali Saidi 1546d8208b ARM: SE needs a definition for PageTable::serialize/unserialize 2010-06-02 12:58:16 -05:00
Ali Saidi d2ba9243f5 ARM: Add BKPT instruction 
--HG--
rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa
 2010-06-02 12:58:16 -05:00
Ali Saidi b8ec214553 ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
Ali Saidi 3aea20d143 ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs. 2010-06-02 12:58:16 -05:00
Gabe Black 237c0617a0 ARM: Implement conversion to/from half precision. 2010-06-02 12:58:16 -05:00
Gabe Black 04e196f422 ARM: Clean up VFP 2010-06-02 12:58:16 -05:00
Gabe Black 0fe0390f73 ARM: Clean up the implementation of the VFP instructions. 2010-06-02 12:58:16 -05:00
Gabe Black c919ab5b4f ARM: Fix double precision load/store multiple decrement. 
When decrementing, the higher addressed half of a double word is at a 4 byte
smaller displacement.
 2010-06-02 12:58:15 -05:00
Gabe Black 92bdf57be4 ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing. 2010-06-02 12:58:15 -05:00
Gabe Black 4398075254 ARM: Make various bits of the FP control registers read only. 2010-06-02 12:58:15 -05:00
Gabe Black 2d08b8de91 ARM: Implement the version of VMRS that writes to the APSR. 2010-06-02 12:58:15 -05:00
Gabe Black 57c4d37c10 ARM: Ignore reads and writes to DCIMVAC. 2010-06-02 12:58:15 -05:00
Gabe Black fd37095fa6 ARM: Make MPIDR return 0 and ignore writes. 2010-06-02 12:58:15 -05:00
Gabe Black 49b7088b91 ARM: Implement the VCMPE instruction. 2010-06-02 12:58:15 -05:00
Gabe Black 23ba9c7b96 ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR. 2010-06-02 12:58:15 -05:00
Gabe Black 1fda944716 ARM: Fix saturation of VCVT from fp to integer. 2010-06-02 12:58:15 -05:00
Gabe Black 347ab6c704 ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after. 2010-06-02 12:58:15 -05:00
Gabe Black fd82a47b96 ARM: Implement flush to zero for destinations as well. 2010-06-02 12:58:15 -05:00
Gabe Black 186273e5f3 ARM: Fix up nans to match ARM's expected behavior. 2010-06-02 12:58:15 -05:00