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Author SHA1 Message Date
Nathan Binkert e141cb7441 flags: Change naming of functions to be clearer 2008-12-06 14:18:18 -08:00
Ali Saidi dd788a23c9 IGbE: Add support for newer 8257x based Intel NICs 2008-12-05 13:58:22 -05:00
Ali Saidi 400e516261 IGbE: Add support for TCP segment offload 2008-12-05 13:58:21 -05:00
Ali Saidi aab595a306 INet: Allow updating on id, len, seq, and flag field for TCP segment offload 2008-12-05 13:58:21 -05:00
Lisa Hsu 854aa60fdc Automated merge with ssh://m5sim.org//repo/m5 2008-12-05 12:11:46 -05:00
Lisa Hsu f1430941cf This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. 2008-12-05 12:09:29 -05:00
Lisa Hsu e2c7618e50 This patch pulls out the auxiliary vector struct from individual ISA 
LiveProcesses to the base LiveProcess definition so anyone can use them.
 2008-12-04 18:03:35 -05:00
Nathan Binkert 74f10be526 cprintf: support a configurable width and precision ("*" in printf) 2008-12-03 04:57:54 -08:00
Steve Reinhardt 041ca19edc Assume files w/o obvious OS are Linux (with warning) 
instead of giving a fatal error.
 2008-11-20 19:08:46 -08:00
Steve Reinhardt ce4c9a7c10 Sort trace flags before printing them. 2008-11-17 12:41:50 -08:00
Clint Smullen 3087be945d Output: Include gzstream package to allow automatically-gzipped output 
The gzstream package provides an ostream-interface for writing gzipped files.
The package comes from:
    http://www.cs.unc.edu/Research/compgeom/gzstream/
And is distributed under the LGPL license. Both the license and version
information has been preservered, though all other files in the package have
been purged. Minor modifications to the code have been made. The output module
detects when a filename ends in .gz and constructs an ogzstream object instead
of an ofstream object. This works for both the create(...) and find(...)
commands. Additionally, since gzstream objects needs to be closed to ensure
proper file termination, I have the output deconstructor deleting all ostream's
that it manages on behalf of find(...). At the moment, the only output file
that I know this functionality works for is stats, i.e. by specifying
"--stats-file=m5stats.txt.gz" on the command line.
 2008-11-15 23:42:11 -05:00
Steve Reinhardt 4514f565e3 syscalls: fix latent brk/obreak bug. 
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.
 2008-11-15 09:30:10 -08:00
Steve Reinhardt 640b415688 Cache: get rid of obsolete Tag methods. 
I think readData() and writeData() were used for Erik's compression
work, but that code is gone, these aren't called anymore, and they
don't even really do what their names imply.
 2008-11-14 14:14:35 -08:00
Nathan Binkert 5711282f87 Fix a bunch of bugs I introduced when I changed the flags stuff for packets. 
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out.  I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
 2008-11-14 04:55:30 -08:00
Gabe Black 7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. 2008-11-13 23:30:37 -08:00
Nathan Binkert 4d64d7664c SCons: Allow top level directory of EXTRAS able to contain SConscripts. 
The current EXTRAS will fail if the top level directory pointed to by EXTRAS
has a SConscript file in it.  We allow this by including the directory name
of the EXTRA in the build directory which prevents a clash between
src/SConscript and extra/SConscript. Maintain compatibility with older uses
of EXTRAS by adding a -I for each top level extra directory.
 2008-11-10 11:51:18 -08:00
Nathan Binkert eb5d9ba72b pseudo inst: Add rpns (read processor nanoseconds) instruction. 
This instruction basically returns the number of nanoseconds that the CPU
has been running.
 2008-11-10 11:51:18 -08:00
Nathan Binkert c25d966b06 Clean up the SimpleTimingPort class a little bit. 
Move the constructor into the .cc file and get rid of the typedef for
SendEvent.
 2008-11-10 11:51:18 -08:00
Nathan Binkert ea70a44c9f clean: Move some stuff from the hh file to the cc file. 2008-11-10 11:51:18 -08:00
Nathan Binkert 4e02e7c217 python: Fix the reference counting for python events placed on the eventq. 
We need to add a reference when an object is put on the C++ queue, and remove
a reference when the object is removed from the queue.  This was not happening
before and caused a memory problem.
 2008-11-10 11:51:18 -08:00
Clint Smullen 1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu. 
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
 2008-11-10 11:51:18 -08:00
Nathan Binkert 9c49bc7b00 mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
Nathan Binkert 3535d746ab style: clean up the Packet stuff 2008-11-10 11:51:17 -08:00
Nathan Binkert 2dd699ed3d flags: Provide an object for managing boolean flags for an object. 
In many cases it might be preferable to use bitset, but this object
allows the user more easily manipulate groups of flags because the
underlying type (e.g. uint64_t) is exposed.
 2008-11-10 11:51:17 -08:00
Nathan Binkert 194f0310d3 safe_cast: add a new cast function for casts that should always succeed. 
In DEBUG mode, this does a dynamic_cast and asserts that the result is
non null.  Otherwise, it just does a static_cast.  Again, this is only
intended for cases where the cast should always succeed and what's
desired is a debugging check to make sure.
 2008-11-10 11:51:17 -08:00
Steve Reinhardt 27e8f3c98a DmaDevice: fix minor type in error message. 2008-11-10 14:45:31 -08:00
Steve Reinhardt 63127cbf37 mem: Assert that requests have non-negative size. 
Would have saved me much debugging time if these
had been in there previously.
 2008-11-10 14:11:07 -08:00
Steve Reinhardt 42bd460d7f Cache: Refactor packet forwarding a bit. 
Makes adding write-through operations easier.
 2008-11-10 14:10:28 -08:00
Gabe Black 846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. 2008-11-09 21:56:28 -08:00
Gabe Black 8c15518f30 X86: Fix completeAcc get call. 2008-11-09 21:55:43 -08:00
Gabe Black 909380f3ee X86: Make the timing simple CPU handle variable length instructions. 2008-11-09 21:55:01 -08:00
Nathan Binkert 44839d6b71 Fix a few more places where the context stuff wasn't changed 2008-11-05 07:20:03 -08:00
Lisa Hsu 46b56bb7b6 Fix SPARC_FS compile 2008-11-05 16:19:17 -05:00
Lisa Hsu 07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending 
on the order in which it's registered with the system.  To make them match,
here is a little change.
 2008-11-05 15:30:49 -05:00
Lisa Hsu c68032ddcb decouple eviction from insertion in the cache. 2008-11-04 11:35:58 -05:00
Lisa Hsu 4ab52cb986 Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used. 2008-11-04 11:35:57 -05:00
Lisa Hsu dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate 
redundancies with threadId() as their replacement.
 2008-11-04 11:35:42 -05:00
Lisa Hsu d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used, 
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
 2008-11-02 21:57:07 -05:00
Lisa Hsu 67fda02dda Make it so that all thread contexts are registered with the System, even in 
SE.  Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
 2008-11-02 21:57:06 -05:00
Lisa Hsu c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered 
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
 2008-11-02 21:56:57 -05:00
Clint Smullen 95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. 
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
 2008-10-27 18:18:04 -04:00
Clint Smullen cfa32d8de7 Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python. 
Signed-off By: Ali Saidi
 2008-10-27 19:46:01 -04:00
Lisa Hsu 8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in 
comments.
 2008-10-23 16:49:17 -04:00
Lisa Hsu 546a6c0c1b probe function no longer used anywhere. 2008-10-23 16:49:13 -04:00
Lisa Hsu 7a28ab2d18 remove the totally obsolete split cache 2008-10-23 16:11:28 -04:00
Nathan Binkert 9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes 
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
 2008-10-20 16:22:59 -04:00
Lisa Hsu 4fac54f227 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 2008-10-19 22:50:53 -04:00
Nathan Binkert 9b8011e255 need to add packet_access.hh in order to get tempalte definition 2008-10-16 22:22:47 -07:00
Nathan Binkert 81f5da1e89 get rid of local variable that's only used in an assert so fast compiles 2008-10-16 22:22:17 -07:00
Lisa Hsu 101c2d9174 Automated merge with ssh://daystrom.m5sim.org//z/repo/m5 2008-10-16 14:16:26 -04:00
Lisa Hsu 90e40ca982 This function declaration isn't used anywhere. 
HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed
src/mem/cache/cache.hh
 2008-10-14 17:22:03 -04:00
Nathan Binkert 5b07448cf1 eventq: make python events actually work 2008-10-14 09:34:11 -07:00
Nathan Binkert ff2eea1ba3 eventq: revert code for unserializing events. 
Since I never implemented a proper solution, put it back to something that
at least works for now.  Once I add more event queues, I'll have to really
fix this though
 2008-10-14 09:33:52 -07:00
Gabe Black 809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black 34ca72d16d Get rid of some commented out code. 2008-10-12 23:50:22 -07:00
Gabe Black 3c4567f2a6 X86: Set the delayed commit flag in x86 microops appropriately. 2008-10-12 23:29:10 -07:00
Gabe Black 33ebd04474 X86: Make the local APIC timer event generate an interrupt. 2008-10-12 23:28:49 -07:00
Gabe Black bdc28d793d X86: Implement the EOI register in the local APIC. 2008-10-12 23:28:11 -07:00
Gabe Black fd37688294 X86: Add some DPRINTFs to the local APIC. 2008-10-12 23:27:45 -07:00
Gabe Black be6055e0f2 X86: Make auto eoi mode work in the I8259 PIC. 2008-10-12 23:27:08 -07:00
Gabe Black fb5bb434a9 X86: Make non-specific EOI commands work. 2008-10-12 23:25:48 -07:00
Gabe Black 8e664f3959 X86: Make the I8259 PIC accept a specific EOI command. 2008-10-12 23:22:58 -07:00
Gabe Black e3004c579f X86: Fix the segment setting code in IRET, and make it restore the flags. 2008-10-12 23:05:22 -07:00
Gabe Black 349a155b6e X86: Panic when an unimplemented fault is invoked, rather than spinning forever 2008-10-12 23:00:28 -07:00
Gabe Black 564eda827b X86: Implement the swapgs instruction. 2008-10-12 23:00:07 -07:00
Gabe Black a2e0d539d8 X86: Add wrval/rdval microops for reading significant miscregs. 2008-10-12 22:55:55 -07:00
Gabe Black 9e8e2f9ec6 X86: Make the x86 interrupt fault kick off the interrupt microcode. 2008-10-12 22:42:10 -07:00
Gabe Black 4c19c56a77 X86: Implement entering an interrupt in microcode. 2008-10-12 22:42:03 -07:00
Gabe Black f813a4be49 X86: Make sure register microops set fault rather than returning one. 2008-10-12 22:24:06 -07:00
Gabe Black 961b40cdb5 X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors. 2008-10-12 22:16:53 -07:00
Gabe Black 989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black 6074b1abf2 X86: Implement local labels for the ROM that actually refer into the ROM. 2008-10-12 20:44:11 -07:00
Gabe Black 6b46e5204d X86: Implement the chks check of interrupt gate target code segments. 2008-10-12 20:38:22 -07:00
Gabe Black 30feb90c1c X86: Add a check type for interrupt gates. 2008-10-12 20:33:37 -07:00
Gabe Black 15f5bb3055 X86: Fix chks checking the submode for stack segments. 2008-10-12 20:29:52 -07:00
Gabe Black 9e1fe2050a X86: Let segment manipulation microops be conditional. 2008-10-12 20:25:06 -07:00
Gabe Black e9158d763a X86: Let the microassembler know about the microcode only H segment. 2008-10-12 20:17:38 -07:00
Gabe Black 223fc41c07 X86: Fix the rdbase microop 2008-10-12 20:07:46 -07:00
Gabe Black 0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black cefb768131 X86: Create a handy way to access labels from the ROM in microcode. 2008-10-12 17:52:51 -07:00
Gabe Black e5f8092467 X86: Make X86's microcode ROM actually do something. 2008-10-12 17:48:44 -07:00
Gabe Black c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black 2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black 6fd4eff68f X86: Create an eret microop which returns from ROM to combinational decoding. 2008-10-12 15:53:04 -07:00
Gabe Black 4aa18aa800 X86: Make Br never report itself as the last microop. 2008-10-12 15:43:35 -07:00
Gabe Black 77c0e1d110 X86: Create a SeqOp class of microops and make Br one of them. 2008-10-12 15:33:17 -07:00
Gabe Black a76c4b8ca1 X86: Implement CPUID with a magical function instead of microcode. 2008-10-12 15:31:28 -07:00
Gabe Black d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black 3a1905157e X86: Create a mechanism for the IO APIC to access I8259 vectors. 2008-10-12 13:54:57 -07:00
Gabe Black c35da8e495 X86: Actually use the extra vector bits we get from ICW2. 2008-10-12 13:51:48 -07:00
Gabe Black ec9d3aad71 X86: Make the local APIC process interrupts and send them to the CPU. 2008-10-12 13:45:21 -07:00
Gabe Black 876f4845f2 X86: Make the local APIC handle interrupt messages from the IO APIC. 2008-10-12 13:44:24 -07:00
Gabe Black 4d5c7f7038 X86: Change the default value for the IO APIC redirection table. 2008-10-12 13:35:26 -07:00
Gabe Black 3420ad7644 X86: Make the bases for x86 fault class public. 2008-10-12 13:29:26 -07:00
Gabe Black 557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black e459013182 Create a message port for sending messages as apposed to reading/writing a memory range. 2008-10-12 12:08:51 -07:00
Gabe Black e0f137a87c X86: Add a LocalApic trace flag. 2008-10-12 12:07:25 -07:00
Gabe Black 42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00