Mostly cleanup of mpy_importer.mpy_parse().
python/m5/__init__.py:
Move panic() up to top in case we want to use it
in mpy_importer (though I ended up not doing that
after all).
python/m5/config.py:
Add a couple of comments and a check for expressions
like parent.any.foo (which is illegal).
--HG--
extra : convert_revision : dfc99ac9b1a2d91a736ca0b773b6d3c528a4f3cc
python/m5/config.py:
Allow proxies to refer to other proxies and resolve by recurseivly calling unproxy().
Not sure this works completely (since I don't have any examples to test it on)
but it doesn't seem to break any existing config scripts.
--HG--
extra : convert_revision : d7fc272d0777d85f89104dfb5d1c5e4d8ddd6d6f
arch/alpha/alpha_tru64_process.cc:
sim/process.cc:
sim/process.hh:
Add an address range for the nxm
sim/syscall_emul.hh:
Check to make sure that if we have an nxm config space that the mmap hasn't grown into it
--HG--
extra : convert_revision : e479e5240080ae488080d228bafea488835d6e77
python/m5/config.py:
- Enhanced Proxy class now supports subscripting, e.g.,
parent.cpu[0] or even parent.cpu[0].icache.
- Proxy also supports multiplication (e.g., parent.cycle * 3),
though this feature has not been tested.
- Subscript 0 works even on non-lists, so you can safely say
cpu[0] and get the first cpu even if there's only one.
- Changed name of proxy object from 'Super' to 'parent', and
changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').
--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
data too early (before the cache miss completed) and therefore
writing freeded memory after the cache miss completed.
Also removed some spurious setAddr() and setData() calls.
--HG--
extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2
sim/sim_object.cc:
Add a new constructor that can take the params struct and
tweak the old one to create a params struct if we use the
old constructor.
sim/sim_object.hh:
Hard code a Params struct for SimObject that all other params
structs can derive from. Move the name string into the struct
and update the code accordingly. New constructor that takes
the params struct.
--HG--
extra : convert_revision : 30761dab31d7257f9e8c864dcd6cae37309163f2
cpu/base_cpu.cc:
By default we should panic if the system doesn't explicitly support
switchover.
--HG--
extra : convert_revision : 4da2ec316d609cfb351fc5ceaa6d8fe36be14d4e
arch/alpha/alpha_tru64_process.cc:
g++ 3.4 fixes. Must cast to an int prior to returning value.
--HG--
extra : convert_revision : d8ccfd7aa7ca00d9bc2d76cff014b9f142d10640
remove addr from pciconfig objects
and update Monet configuration for ron's changes
python/m5/objects/Pci.mpy:
I was a little over zelous in my removal of addr, this one should have stayed
--HG--
extra : convert_revision : 6c94b11d4c63d50ffe5568b16a131a4105654126
multiple SConscript files to SConstruct.
build/SConstruct:
Add SRCDIR/python to sys.path here.
python/SConscript:
Move adding SRCDIR/python to sys.path to SConstruct.
--HG--
extra : convert_revision : f598d670650f5b4fd501caaf073fe38b44d21855
belongs there since it's so tied in with m5.config).
python/SConscript:
mpy_importer.py now in m5 package
--HG--
extra : convert_revision : 3cd7af4e1cd9338aa6bed5306c824ac5f0965085
