inorder: pipeline stage stats
add idle/run/utilization stats for each pipeline stage
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4d749472e3
commit
ffa9ecb1fa
4 changed files with 55 additions and 62 deletions
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@ -346,6 +346,11 @@ InOrderCPU::regStats()
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.prereq(maxResReqCount);
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#endif
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/* Register for each Pipeline Stage */
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for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
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pipelineStage[stage_num]->regStats();
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}
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/* Register any of the InOrderCPU's stats here.*/
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timesIdled
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.name(name() + ".timesIdled")
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@ -1289,8 +1294,14 @@ InOrderCPU::wakeCPU()
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DPRINTF(Activity, "Waking up CPU\n");
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//@todo: figure out how to count idleCycles correctly
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//idleCycles += (curTick - 1) - lastRunningCycle;
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Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
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idleCycles += extra_cycles;
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for (int stage_num = 0; stage_num < NumStages; stage_num++) {
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pipelineStage[stage_num]->idleCycles += extra_cycles;
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}
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numCycles += extra_cycles;
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mainEventQueue.schedule(&tickEvent, curTick);
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}
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@ -118,9 +118,9 @@ FirstStage::processStage(bool &status_change)
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status_change = checkSignalsAndUpdate(tid) || status_change;
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}
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for (int threadFetched = 0; threadFetched < numFetchingThreads;
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threadFetched++) {
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for (int insts_fetched = 0;
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insts_fetched < stageWidth && canSendInstToStage(1);
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insts_fetched++) {
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ThreadID tid = getFetchingThread(fetchPolicy);
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if (tid >= 0) {
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@ -130,6 +130,13 @@ FirstStage::processStage(bool &status_change)
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DPRINTF(InOrderStage, "No more threads to fetch from.\n");
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}
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}
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if (instsProcessed > 0) {
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++runCycles;
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} else {
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++idleCycles;
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}
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}
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//@TODO: Note in documentation, that when you make a pipeline stage change,
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@ -197,7 +204,6 @@ FirstStage::processInsts(ThreadID tid)
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}
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sendInstToNextStage(inst);
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//++stageProcessedInsts;
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}
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// Record that stage has written to the time buffer for activity
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@ -72,41 +72,27 @@ PipelineStage::init(Params *params)
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std::string
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PipelineStage::name() const
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{
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return cpu->name() + ".stage-" + to_string(stageNum);
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return cpu->name() + ".stage-" + to_string(stageNum);
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}
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void
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PipelineStage::regStats()
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{
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/* stageIdleCycles
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.name(name() + ".IdleCycles")
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.desc("Number of cycles stage is idle")
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.prereq(stageIdleCycles);
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stageBlockedCycles
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.name(name() + ".BlockedCycles")
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.desc("Number of cycles stage is blocked")
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.prereq(stageBlockedCycles);
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stageRunCycles
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.name(name() + ".RunCycles")
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.desc("Number of cycles stage is running")
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.prereq(stageRunCycles);
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stageUnblockCycles
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.name(name() + ".UnblockCycles")
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.desc("Number of cycles stage is unblocking")
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.prereq(stageUnblockCycles);
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stageSquashCycles
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.name(name() + ".SquashCycles")
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.desc("Number of cycles stage is squashing")
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.prereq(stageSquashCycles);
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stageProcessedInsts
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.name(name() + ".ProcessedInsts")
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.desc("Number of instructions handled by stage")
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.prereq(stageProcessedInsts);
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stageSquashedInsts
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.name(name() + ".SquashedInsts")
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.desc("Number of squashed instructions handled by stage")
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.prereq(stageSquashedInsts);*/
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idleCycles
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.name(name() + ".idleCycles")
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.desc("Number of cycles 0 instructions are processed.");
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runCycles
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.name(name() + ".runCycles")
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.desc("Number of cycles 1+ instructions are processed.");
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utilization
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.name(name() + ".utilization")
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.desc("Percentage of cycles stage was utilized (processing insts).")
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.precision(6);
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utilization = (runCycles / cpu->numCycles) * 100;
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}
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@ -803,6 +789,12 @@ PipelineStage::processStage(bool &status_change)
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nextStage->size, stageNum + 1);
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}
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if (instsProcessed > 0) {
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++runCycles;
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} else {
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++idleCycles;
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}
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DPRINTF(InOrderStage, "%i left in stage %i incoming buffer.\n", skidSize(),
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stageNum);
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@ -820,12 +812,6 @@ PipelineStage::processThread(bool &status_change, ThreadID tid)
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// continue trying to empty skid buffer
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// check if stall conditions have passed
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if (stageStatus[tid] == Blocked) {
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;//++stageBlockedCycles;
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} else if (stageStatus[tid] == Squashing) {
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;//++stageSquashCycles;
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}
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// Stage should try to process as many instructions as its bandwidth
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// will allow, as long as it is not currently blocked.
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if (stageStatus[tid] == Running ||
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@ -867,8 +853,6 @@ PipelineStage::processInsts(ThreadID tid)
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if (insts_available == 0) {
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DPRINTF(InOrderStage, "[tid:%u]: Nothing to do, breaking out"
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" early.\n",tid);
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// Should I change the status to idle?
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//++stageIdleCycles;
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return;
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}
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@ -892,8 +876,6 @@ PipelineStage::processInsts(ThreadID tid)
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"squashed, skipping.\n",
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tid, inst->seqNum, inst->readPC());
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//++stageSquashedInsts;
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insts_to_stage.pop();
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--insts_available;
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@ -924,7 +906,6 @@ PipelineStage::processInsts(ThreadID tid)
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insts_to_stage.pop();
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//++stageProcessedInsts;
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--insts_available;
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}
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@ -353,24 +353,19 @@ class PipelineStage
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std::vector<ResReqPtr> resources;
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};
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/** Tracks which stages are telling decode to stall. */
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/** Tracks stage/resource stalls */
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Stalls stalls[ThePipeline::MaxThreads];
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//@TODO: Use Stats for the pipeline stages
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/** Stat for total number of idle cycles. */
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//Stats::Scalar stageIdleCycles;
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/** Stat for total number of blocked cycles. */
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//Stats::Scalar stageBlockedCycles;
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/** Stat for total number of normal running cycles. */
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//Stats::Scalar stageRunCycles;
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/** Stat for total number of unblocking cycles. */
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//Stats::Scalar stageUnblockCycles;
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/** Stat for total number of squashing cycles. */
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//Stats::Scalar stageSquashCycles;
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/** Stat for total number of staged instructions. */
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//Stats::Scalar stageProcessedInsts;
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/** Stat for total number of squashed instructions. */
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//Stats::Scalar stageSquashedInsts;
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/** Number of cycles 0 instruction(s) are processed. */
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Stats::Scalar idleCycles;
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/** Number of cycles 1+ instructions are processed. */
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Stats::Scalar runCycles;
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/** Percentage of cycles 1+ instructions are processed. */
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Stats::Formula utilization;
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};
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#endif
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