From 9ad24e22481665ae626b0e4ed44e2eea91c1b553 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Mar 2007 13:56:09 -0400 Subject: [PATCH 1/7] move hver code to ua2005.cc src/arch/sparc/miscregfile.cc: this code should be in readFSreg src/arch/sparc/ua2005.cc: move code froh miscregfile to ua2005.cc --HG-- extra : convert_revision : fa450b04ad73ab6f6e25d66fa0368054263f09f9 --- src/arch/sparc/miscregfile.cc | 8 -------- src/arch/sparc/ua2005.cc | 8 +++++++- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 20bc4ae5d..f3be1c4c2 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -231,14 +231,6 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return hintp; case MISCREG_HTBA: return htba; - case MISCREG_HVER: - // XXX set to match Legion - return ULL(0x3e) << 48 | - ULL(0x23) << 32 | - ULL(0x20) << 24 | - //MaxGL << 16 | XXX For some reason legion doesn't set GL - MaxTL << 8 | - (NWindows -1) << 0; case MISCREG_STRAND_STS_REG: return strandStatusReg; case MISCREG_HSTICK_CMPR: diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 439f38457..865280038 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -235,7 +235,13 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) case MISCREG_HTBA: return readRegNoEffect(miscReg) & ULL(~0x7FFF); case MISCREG_HVER: - return NWindows | MaxTL << 8 | MaxGL << 16; + // XXX set to match Legion + return ULL(0x3e) << 48 | + ULL(0x23) << 32 | + ULL(0x20) << 24 | + //MaxGL << 16 | XXX For some reason legion doesn't set GL + MaxTL << 8 | + (NWindows -1) << 0; case MISCREG_STRAND_STS_REG: System *sys; From 885b4f26bb105bf9ad87c252b5bd24e83730fc3c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Mar 2007 14:13:52 -0400 Subject: [PATCH 2/7] Get rid of those pesky valgrind warnings, Conditional jump or move depends on uninitialised value(s), in the stats package --HG-- extra : convert_revision : d3a508fc98df4eb8160a211a306be6ab241a4ce8 --- src/base/stats/text.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc index 66c5955d7..a018c4837 100644 --- a/src/base/stats/text.cc +++ b/src/base/stats/text.cc @@ -251,6 +251,7 @@ VectorPrint::operator()(std::ostream &stream) const ScalarPrint print; print.name = name; print.desc = desc; + print.compat = compat; print.precision = precision; print.descriptions = descriptions; print.flags = flags; From 6415c47a5b196beb16ee56c8cb772dd3fd53b687 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 12 Mar 2007 13:15:32 -0500 Subject: [PATCH 3/7] Fix some of the memory leaks related to writebacks src/cpu/memtest/memtest.cc: Add the [] to a delete to make it work correctly src/mem/cache/cache_impl.hh: Fix one of the memory leaks --HG-- extra : convert_revision : 64c7465c68a084efe38a62419205518b24d852a7 --- src/cpu/memtest/memtest.cc | 2 +- src/mem/cache/cache_impl.hh | 14 ++++++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 8b3e9a11e..607cf1066 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -369,7 +369,7 @@ MemTest::tick() //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { - delete result; + delete [] result; delete req; return; } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 056f6033f..d8aab0e58 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -570,8 +570,10 @@ Cache::access(PacketPtr &pkt) } } while (!writebacks.empty()) { - missQueue->doWriteback(writebacks.front()); + PacketPtr wbPkt = writebacks.front(); + missQueue->doWriteback(wbPkt); writebacks.pop_front(); + delete wbPkt; } DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(), @@ -721,8 +723,10 @@ Cache::handleResponse(PacketPtr &pkt) blk = handleFill(blk, (MSHR*)pkt->senderState, new_state, writebacks, pkt); while (!writebacks.empty()) { - missQueue->doWriteback(writebacks.front()); - writebacks.pop_front(); + PacketPtr wbPkt = writebacks.front(); + missQueue->doWriteback(wbPkt); + writebacks.pop_front(); + delete wbPkt; } } missQueue->handleResponse(pkt, curTick + hitLatency); @@ -1040,8 +1044,10 @@ return 0; // There was a cache hit. // Handle writebacks if needed while (!writebacks.empty()){ - memSidePort->sendAtomic(writebacks.front()); + PacketPtr wbPkt = writebacks.front(); + memSidePort->sendAtomic(wbPkt); writebacks.pop_front(); + delete wbPkt; } hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; From 2a02087eb52e12e16e9da74e929e875ae07519ec Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Mon, 12 Mar 2007 15:59:54 -0500 Subject: [PATCH 4/7] Clean up more memory leaks --HG-- extra : convert_revision : 32d1b23200752fe5fcdcbafb586f50bbe6db3bf3 --- src/mem/cache/cache_impl.hh | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index d8aab0e58..5c6ab0950 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -583,12 +583,7 @@ Cache::access(PacketPtr &pkt) // Hit hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; // clear dirty bit if write through - if (pkt->needsResponse()) - respond(pkt, curTick+lat); - if (pkt->cmd == MemCmd::Writeback) { - //Signal that you can kill the pkt/req - pkt->flags |= SATISFIED; - } + respond(pkt, curTick+lat); return true; } @@ -606,14 +601,14 @@ Cache::access(PacketPtr &pkt) if (pkt->flags & SATISFIED) { // happens when a store conditional fails because it missed // the cache completely - if (pkt->needsResponse()) - respond(pkt, curTick+lat); + respond(pkt, curTick+lat); } else { missQueue->handleMiss(pkt, size, curTick + hitLatency); } - if (pkt->cmd == MemCmd::Writeback) { + if (!pkt->needsResponse()) { //Need to clean up the packet on a writeback miss, but leave the request + //for the next level. delete pkt; } From 8d38dd32311468254c0839ae8f0797f3f824df05 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Mar 2007 17:23:08 -0400 Subject: [PATCH 5/7] remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault --HG-- extra : convert_revision : 5e4c2ec753372fd0569734d3ddb0c8690409ca16 --- src/base/trace.cc | 32 +++++++++++++++----------------- src/cpu/pc_event.cc | 2 -- src/sim/eventq.cc | 1 - 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/src/base/trace.cc b/src/base/trace.cc index 2dde1f688..0a7e6e833 100644 --- a/src/base/trace.cc +++ b/src/base/trace.cc @@ -192,22 +192,20 @@ dumpStatus() // add a set of functions that can easily be invoked from gdb -extern "C" { - void - setTraceFlag(const char *string) - { - Trace::changeFlag(string, true); - } +void +setTraceFlag(const char *string) +{ + Trace::changeFlag(string, true); +} - void - clearTraceFlag(const char *string) - { - Trace::changeFlag(string, false); - } +void +clearTraceFlag(const char *string) +{ + Trace::changeFlag(string, false); +} - void - dumpTraceStatus() - { - Trace::dumpStatus(); - } -/* extern "C" */ } +void +dumpTraceStatus() +{ + Trace::dumpStatus(); +} diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index 7ab8bfcb8..438218df2 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -138,14 +138,12 @@ BreakPCEvent::process(ThreadContext *tc) } #if FULL_SYSTEM -extern "C" void sched_break_pc_sys(System *sys, Addr addr) { new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true); } -extern "C" void sched_break_pc(Addr addr) { diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc index bcd0d3df3..65e115256 100644 --- a/src/sim/eventq.cc +++ b/src/sim/eventq.cc @@ -222,7 +222,6 @@ EventQueue::dump() cprintf("============================================================\n"); } -extern "C" void dumpMainQueue() { From 74db8adfbc5e136b55d2f5ea54d49f67b15d7fea Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Mar 2007 20:16:13 -0400 Subject: [PATCH 6/7] call ccprintf() with the appropriate argument types so we don't recuse forever --HG-- extra : convert_revision : 5366be897d1193cf9e93b1fcd0689d19783f73a8 --- src/base/cprintf.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/base/cprintf.hh b/src/base/cprintf.hh index 7f8e33367..cff73a228 100644 --- a/src/base/cprintf.hh +++ b/src/base/cprintf.hh @@ -143,20 +143,20 @@ ccprintf(std::ostream &stream, const std::string &format, inline void ccprintf(std::ostream &stream, const std::string &format, CPRINTF_DECLARATION) { - ccprintf(stream, format, VARARGS_ALLARGS); + ccprintf(stream, format.c_str(), VARARGS_ALLARGS); } inline void cprintf(const std::string &format, CPRINTF_DECLARATION) { - ccprintf(std::cout, format, VARARGS_ALLARGS); + ccprintf(std::cout, format.c_str(), VARARGS_ALLARGS); } inline std::string csprintf(const std::string &format, CPRINTF_DECLARATION) { std::stringstream stream; - ccprintf(stream, format, VARARGS_ALLARGS); + ccprintf(stream, format.c_str(), VARARGS_ALLARGS); return stream.str(); } From a068d6db0fff7056abb06bb8a99494b63bd169e1 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 13 Mar 2007 00:05:52 -0400 Subject: [PATCH 7/7] fix interrupting during a quisce on sparc src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5 --- src/arch/sparc/ua2005.cc | 9 +++++++-- src/base/traceflags.py | 1 + src/cpu/simple/base.cc | 2 +- src/dev/sparc/iob.cc | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 865280038..48e97a531 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -195,6 +195,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("No support for setting spec_en bit\n"); setRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { + DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep tc->suspend(); if (tc->getKernelStats()) @@ -307,7 +308,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "stick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { @@ -324,11 +325,15 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) // we're actually at the correct cycle or we need to wait a little while // more int ticks; + if ( tc->status() == ThreadContext::Halted || + tc->status() == ThreadContext::Unallocated) + return; + ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "hstick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { diff --git a/src/base/traceflags.py b/src/base/traceflags.py index cb17d98d3..a36db1963 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -116,6 +116,7 @@ baseFlags = [ 'ISP', 'IdeCtrl', 'IdeDisk', + 'Iob', 'Interrupt', 'LLSC', 'LSQ', diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index f6c109127..9feb09851 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -301,7 +301,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index) BaseCPU::post_interrupt(int_num, index); if (thread->status() == ThreadContext::Suspended) { - DPRINTF(IPI,"Suspended Processor awoke\n"); + DPRINTF(Quiesce,"Suspended Processor awoke\n"); thread->activate(); } } diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index 6bd40b631..e686e51f7 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -192,6 +192,8 @@ Iob::writeIob(PacketPtr pkt) data = pkt->get(); intMan[index].cpu = bits(data,12,8); intMan[index].vector = bits(data,5,0); + DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index, + intMan[index].cpu, intMan[index].vector); return; } @@ -201,11 +203,14 @@ Iob::writeIob(PacketPtr pkt) intCtl[index].mask = bits(data,2,2); if (bits(data,1,1)) intCtl[index].pend = false; + DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index, + intCtl[index].pend, bits(data,2,2)); return; } if (accessAddr == JIntVecAddr) { jIntVec = bits(pkt->get(), 5,0); + DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec); return; } @@ -237,11 +242,15 @@ Iob::writeJBus(PacketPtr pkt) index = (accessAddr - JIntBusyAddr) >> 3; data = pkt->get(); jIntBusy[index].busy = bits(data,5,5); + DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index, + jIntBusy[index].busy); return; } if (accessAddr == JIntABusyAddr) { data = pkt->get(); jIntBusy[cpuid].busy = bits(data,5,5); + DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid, + jIntBusy[cpuid].busy); return; }; @@ -256,6 +265,8 @@ Iob::receiveDeviceInterrupt(DeviceId devid) return; intCtl[devid].mask = true; intCtl[devid].pend = true; + DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n", + devid, intMan[devid].cpu, intMan[devid].vector); ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); } @@ -269,6 +280,8 @@ Iob::generateIpi(Type type, int cpu_id, int vector) switch (type) { case 0: // interrupt + DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n", + cpu_id, vector); ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); break; case 1: // reset @@ -279,9 +292,11 @@ Iob::generateIpi(Type type, int cpu_id, int vector) sys->threadContexts[cpu_id]->activate(); break; case 2: // idle -- this means stop executing and don't wake on interrupts + DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id); sys->threadContexts[cpu_id]->halt(); break; case 3: // resume + DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id); sys->threadContexts[cpu_id]->activate(); break; default: @@ -297,6 +312,9 @@ Iob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) if (jIntBusy[cpu_id].busy) return false; + DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n", + source, cpu_id, jIntVec); + jIntBusy[cpu_id].busy = true; jIntBusy[cpu_id].source = source; jBusData0[cpu_id] = d0;