Eliminate unused PacketPtr from BaseCache's
RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105
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df3fc36fa9
commit
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2 changed files with 3 additions and 9 deletions
10
src/mem/cache/base_cache.cc
vendored
10
src/mem/cache/base_cache.cc
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@ -229,7 +229,6 @@ BaseCache::RequestEvent::RequestEvent(CachePort *_cachePort, Tick when)
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: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
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{
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this->setFlags(AutoDelete);
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pkt = NULL;
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schedule(when);
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}
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@ -266,7 +265,7 @@ BaseCache::RequestEvent::process()
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return;
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}
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pkt = cachePort->cache->getPacket();
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PacketPtr pkt = cachePort->cache->getPacket();
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MSHR* mshr = (MSHR*) pkt->senderState;
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//Copy the packet, it may be modified/destroyed elsewhere
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PacketPtr copyPkt = new Packet(*pkt);
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@ -288,7 +287,6 @@ BaseCache::RequestEvent::process()
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DPRINTF(CachePort, "%s still more MSHR requests to send\n",
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cachePort->name());
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//Still more to issue, rerequest in 1 cycle
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pkt = NULL;
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this->schedule(curTick+1);
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}
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}
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@ -296,7 +294,7 @@ BaseCache::RequestEvent::process()
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{
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//CSHR
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assert(cachePort->cache->doSlaveRequest());
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pkt = cachePort->cache->getCoherencePacket();
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PacketPtr pkt = cachePort->cache->getCoherencePacket();
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MSHR* cshr = (MSHR*) pkt->senderState;
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bool success = cachePort->sendTiming(pkt);
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cachePort->cache->sendCoherenceResult(pkt, cshr, success);
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@ -308,7 +306,6 @@ BaseCache::RequestEvent::process()
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DPRINTF(CachePort, "%s still more CSHR requests to send\n",
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cachePort->name());
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//Still more to issue, rerequest in 1 cycle
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pkt = NULL;
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this->schedule(curTick+1);
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}
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}
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@ -323,7 +320,6 @@ BaseCache::RequestEvent::description()
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BaseCache::ResponseEvent::ResponseEvent(CachePort *_cachePort)
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: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
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{
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pkt = NULL;
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}
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void
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@ -331,7 +327,7 @@ BaseCache::ResponseEvent::process()
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{
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assert(cachePort->transmitList.size());
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assert(cachePort->transmitList.front().first <= curTick);
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pkt = cachePort->transmitList.front().second;
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PacketPtr pkt = cachePort->transmitList.front().second;
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cachePort->transmitList.pop_front();
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if (!cachePort->transmitList.empty()) {
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Tick time = cachePort->transmitList.front().first;
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2
src/mem/cache/base_cache.hh
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2
src/mem/cache/base_cache.hh
vendored
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@ -120,7 +120,6 @@ class BaseCache : public MemObject
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struct RequestEvent : public Event
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{
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CachePort *cachePort;
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PacketPtr pkt;
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RequestEvent(CachePort *_cachePort, Tick when);
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void process();
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@ -130,7 +129,6 @@ class BaseCache : public MemObject
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struct ResponseEvent : public Event
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{
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CachePort *cachePort;
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PacketPtr pkt;
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ResponseEvent(CachePort *_cachePort);
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void process();
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