ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
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@ -66,7 +66,7 @@ let {{
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["IsNonSpeculative", "IsQuiesce"])
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header_output += BasicDeclare.subst(quiesceIop)
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decoder_output += BasicConstructor.subst(quiesceIop)
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exec_output += PredOpExecute.subst(quiesceIop)
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exec_output += QuiescePredOpExecute.subst(quiesceIop)
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quiesceNsCode = '''
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#if FULL_SYSTEM
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@ -80,7 +80,7 @@ let {{
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["IsNonSpeculative", "IsQuiesce"])
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header_output += BasicDeclare.subst(quiesceNsIop)
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decoder_output += BasicConstructor.subst(quiesceNsIop)
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exec_output += PredOpExecute.subst(quiesceNsIop)
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exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
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quiesceCyclesCode = '''
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#if FULL_SYSTEM
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@ -94,7 +94,7 @@ let {{
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["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"])
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header_output += BasicDeclare.subst(quiesceCyclesIop)
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decoder_output += BasicConstructor.subst(quiesceCyclesIop)
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exec_output += PredOpExecute.subst(quiesceCyclesIop)
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exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
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quiesceTimeCode = '''
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#if FULL_SYSTEM
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@ -491,10 +491,13 @@ let {{
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wfeCode = '''
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#if FULL_SYSTEM
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if (SevMailbox)
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if (SevMailbox) {
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SevMailbox = 0;
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else
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PseudoInst::quiesceSkip(xc->tcBase());
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}
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else {
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PseudoInst::quiesce(xc->tcBase());
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}
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#endif
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'''
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wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
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@ -502,7 +505,7 @@ let {{
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["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
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header_output += BasicDeclare.subst(wfeIop)
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decoder_output += BasicConstructor.subst(wfeIop)
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exec_output += PredOpExecute.subst(wfeIop)
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exec_output += QuiescePredOpExecute.subst(wfeIop)
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wfiCode = '''
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#if FULL_SYSTEM
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@ -511,22 +514,25 @@ let {{
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'''
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wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
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{ "code" : wfiCode, "predicate_test" : predicateTest },
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["IsNonSpeculative", "IsQuiesce"])
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["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
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header_output += BasicDeclare.subst(wfiIop)
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decoder_output += BasicConstructor.subst(wfiIop)
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exec_output += PredOpExecute.subst(wfiIop)
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exec_output += QuiescePredOpExecute.subst(wfiIop)
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sevCode = '''
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// Need a way for O3 to not scoreboard these accesses as pipe flushes.
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SevMailbox = 1;
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System *sys = xc->tcBase()->getSystemPtr();
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for (int x = 0; x < sys->numContexts(); x++) {
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ThreadContext *oc = sys->getThreadContext(x);
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if (oc != xc->tcBase()) {
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oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
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}
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}
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'''
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sevIop = InstObjParams("sev", "SevInst", "PredOp", \
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{ "code" : sevCode, "predicate_test" : predicateTest },
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["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
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["IsNonSpeculative", "IsSquashAfter"])
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header_output += BasicDeclare.subst(sevIop)
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decoder_output += BasicConstructor.subst(sevIop)
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exec_output += PredOpExecute.subst(sevIop)
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@ -170,6 +170,38 @@ def template PredOpExecute {{
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}
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}};
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def template QuiescePredOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t resTemp = 0;
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resTemp = resTemp;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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} else {
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xc->setPredicate(false);
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#if FULL_SYSTEM
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PseudoInst::quiesceSkip(xc->tcBase());
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#endif
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}
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if (fault == NoFault && machInst.itstateMask != 0&&
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(!isMicroop() || isLastMicroop())) {
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xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
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}
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return fault;
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}
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}};
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def template DataDecode {{
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if (machInst.opcode4 == 0) {
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if (machInst.sField == 0)
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@ -1,4 +1,16 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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@ -85,6 +97,28 @@ quiesce(ThreadContext *tc)
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tc->getKernelStats()->quiesce();
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}
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void
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quiesceSkip(ThreadContext *tc)
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{
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BaseCPU *cpu = tc->getCpuPtr();
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if (!cpu->params()->do_quiesce)
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return;
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EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
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Tick resume = curTick() + 1;
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cpu->reschedule(quiesceEvent, resume, true);
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DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
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cpu->name(), resume);
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tc->suspend();
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if (tc->getKernelStats())
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tc->getKernelStats()->quiesce();
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}
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void
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quiesceNs(ThreadContext *tc, uint64_t ns)
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{
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@ -45,6 +45,7 @@ extern bool doQuiesce;
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#if FULL_SYSTEM
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void arm(ThreadContext *tc);
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void quiesce(ThreadContext *tc);
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void quiesceSkip(ThreadContext *tc);
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void quiesceNs(ThreadContext *tc, uint64_t ns);
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void quiesceCycles(ThreadContext *tc, uint64_t cycles);
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uint64_t quiesceTime(ThreadContext *tc);
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