Remove bus and top level parameters from cache

src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
This commit is contained in:
Ron Dreslinski 2006-10-12 14:21:25 -04:00
parent f89b56b61a
commit fe230ddb8f
3 changed files with 10 additions and 40 deletions

View file

@ -212,10 +212,6 @@ class BaseCache : public MemObject
protected:
/** True if this cache is connected to the CPU. */
bool topLevelCache;
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@ -337,7 +333,7 @@ class BaseCache : public MemObject
*/
BaseCache(const std::string &name, Params &params)
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
slaveRequests(0), blkSize(params.blkSize),
missCount(params.maxMisses)
{
//Start ports at null if more than one is created we should panic
@ -357,15 +353,6 @@ class BaseCache : public MemObject
return blkSize;
}
/**
* Returns true if this cache is connect to the CPU.
* @return True if this is a L1 cache.
*/
bool isTopLevel()
{
return topLevelCache;
}
/**
* Returns true if the cache is blocked for accesses.
*/
@ -561,8 +548,6 @@ class BaseCache : public MemObject
*/
void respondToSnoop(Packet *pkt, Tick time)
{
// assert("Implement\n" && 0);
// mi->respond(pkt,curTick + hitLatency);
assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
reqMem->schedule(time);
@ -585,15 +570,7 @@ class BaseCache : public MemObject
{
//This is where snoops get updated
AddrRangeList dummy;
// if (!topLevelCache)
// {
cpuSidePort->getPeerAddressRanges(dummy, snoop);
// }
// else
// {
// snoop.push_back(RangeSize(0,-1));
// }
return;
}
}

View file

@ -151,12 +151,7 @@ Cache(const std::string &_name,
doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
hitLatency(params.hitLatency)
{
//FIX BUS POINTERS
// if (params.in == NULL) {
topLevelCache = true;
// }
//PLEASE FIX THIS, BUS SIZES NOT BEING USED
tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
tags->setCache(this);
tags->setPrefetcher(prefetcher);
missQueue->setCache(this);
missQueue->setPrefetcher(prefetcher);
@ -397,7 +392,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
if (coherence->hasProtocol()) { //@todo Move this into handle bus req
//If we find an mshr, and it is in service, we need to NACK or invalidate
if (mshr) {
if (mshr->inService) {

View file

@ -68,7 +68,6 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
if (pkt->isInvalidate()) {
DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
pkt->getAddr(), blk);
if (!cache->isTopLevel()) {
// Forward to other caches
Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
cshrs.allocate(tmp);
@ -76,7 +75,6 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
if (cshrs.isFull()) {
cache->setBlockedForSnoop(Blocked_Coherence);
}
}
} else {
if (blk) {
new_state = blk->status;