ARM: Make MPIDR return 0 and ignore writes.
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49b7088b91
commit
fd37095fa6
2 changed files with 6 additions and 3 deletions
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@ -155,6 +155,8 @@ namespace ArmISA
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mvfr1.vfpHalfPrecision = 1;
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miscRegs[MISCREG_MVFR1] = mvfr1;
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miscRegs[MISCREG_MPIDR] = 0;
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//XXX We need to initialize the rest of the state.
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}
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@ -296,6 +298,7 @@ namespace ArmISA
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MPIDR:
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return;
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}
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return setMiscRegNoEffect(misc_reg, newVal);
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@ -128,10 +128,10 @@ namespace ArmISA
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MISCREG_IFSR,
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MISCREG_DFAR,
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MISCREG_IFAR,
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MISCREG_MPIDR,
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MISCREG_CP15_UNIMP_START,
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MISCREG_CTR = MISCREG_CP15_UNIMP_START,
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MISCREG_TCMTR,
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MISCREG_MPIDR,
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MISCREG_ID_PFR0,
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MISCREG_ID_PFR1,
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MISCREG_ID_DFR0,
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@ -203,8 +203,8 @@ namespace ArmISA
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"itlbiall", "itlbimva", "itlbiasid",
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"dtlbiall", "dtlbimva", "dtlbiasid",
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"tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
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"dfsr", "ifsr", "dfar", "ifar",
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"ctr", "tcmtr", "mpidr",
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"dfsr", "ifsr", "dfar", "ifar", "mpidr",
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"ctr", "tcmtr",
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"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
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"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
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"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
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