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Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.

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Gabe Black 2011-02-03 20:56:27 -08:00
parent 00f24ae92c
commit fd26707731
1 changed files with 8 additions and 1 deletions
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7
configs/example/fs.py
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@ -153,6 +153,13 @@ if options.caches or options.l2cache:
mem_size = bm[0].mem()
else:
mem_size = SysConfig().mem()
# For x86, we need to poke a hole for interrupt messages to get back to the
# CPU. These use a portion of the physical address space which has a
# non-zero prefix in the top nibble. Normal memory accesses have a 0
# prefix.
if buildEnv['TARGET_ISA'] == 'x86':
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
else:
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
test_sys.iocache = IOCache(addr_range=mem_size)