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X86: Remove x86 code that attempted to fix misaligned accesses.

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--HG--
extra : convert_revision : 42f68010e6498aceb7ed25da278093e99150e4df
This commit is contained in:
Gabe Black 2007-08-26 20:30:36 -07:00
parent 24bfda0fdf
commit fcd04f953c
2 changed files with 18 additions and 70 deletions
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38
src/arch/x86/insts/microldstop.hh
View file

@ -106,29 +106,22 @@ namespace X86ISA
Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
int size = dataSize; switch(dataSize)
Addr alignedEA = EA & ~(dataSize - 1);
if (EA != alignedEA)
size *= 2;
switch(size)
{ {
case 1: case 1:
fault = xc->read(alignedEA, (uint8_t&)(Mem.a), flags); fault = xc->read(EA, (uint8_t&)Mem, flags);
break; break;
case 2: case 2:
fault = xc->read(alignedEA, (uint16_t&)(Mem.a), flags); fault = xc->read(EA, (uint16_t&)Mem, flags);
break; break;
case 4: case 4:
fault = xc->read(alignedEA, (uint32_t&)(Mem.a), flags); fault = xc->read(EA, (uint32_t&)Mem, flags);
break; break;
case 8: case 8:
fault = xc->read(alignedEA, (uint64_t&)(Mem.a), flags); fault = xc->read(EA, (uint64_t&)Mem, flags);
break;
case 16:
fault = xc->read(alignedEA, Mem, flags);
break; break;
default: default:
panic("Bad operand size %d for read at %#x.\n", size, EA); panic("Bad operand size %d for read at %#x.\n", dataSize, EA);
} }
return fault; return fault;
} }
@ -137,29 +130,22 @@ namespace X86ISA
Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const
{ {
Fault fault = NoFault; Fault fault = NoFault;
int size = dataSize; switch(dataSize)
Addr alignedEA = EA & ~(dataSize - 1);
if (EA != alignedEA)
size *= 2;
switch(size)
{ {
case 1: case 1:
fault = xc->write((uint8_t&)(Mem.a), alignedEA, flags, 0); fault = xc->write((uint8_t&)Mem, EA, flags, 0);
break; break;
case 2: case 2:
fault = xc->write((uint16_t&)(Mem.a), alignedEA, flags, 0); fault = xc->write((uint16_t&)Mem, EA, flags, 0);
break; break;
case 4: case 4:
fault = xc->write((uint32_t&)(Mem.a), alignedEA, flags, 0); fault = xc->write((uint32_t&)Mem, EA, flags, 0);
break; break;
case 8: case 8:
fault = xc->write((uint64_t&)(Mem.a), alignedEA, flags, 0); fault = xc->write((uint64_t&)Mem, EA, flags, 0);
break;
case 16:
fault = xc->write(Mem, alignedEA, flags, 0);
break; break;
default: default:
panic("Bad operand size %d for write at %#x.\n", size, EA); panic("Bad operand size %d for write at %#x.\n", dataSize, EA);
} }
return fault; return fault;
} }

50
src/arch/x86/isa/microops/ldstop.isa
View file

@ -123,19 +123,7 @@ def template MicroLoadExecute {{
%(ea_code)s; %(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
Twin64_t alignedMem; fault = read(xc, EA, Mem, 0);
fault = read(xc, EA, alignedMem, 0);
int offset = EA & (dataSize - 1);
if(dataSize != 8 || !offset)
{
Mem = bits(alignedMem.a,
(offset + dataSize) * 8 - 1, offset * 8);
}
else
{
Mem = alignedMem.b << (dataSize - offset) * 8;
Mem |= bits(alignedMem.a, dataSize * 8 - 1, offset * 8);
}
if(fault == NoFault) if(fault == NoFault)
{ {
@ -162,9 +150,7 @@ def template MicroLoadInitiateAcc {{
%(ea_code)s; %(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
int offset = EA & (dataSize - 1); fault = read(xc, EA, Mem, 0);
Twin64_t alignedMem;
fault = read(xc, EA, alignedMem, offset);
return fault; return fault;
} }
@ -180,18 +166,8 @@ def template MicroLoadCompleteAcc {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
Twin64_t alignedMem = pkt->get<Twin64_t>(); Mem = pkt->get<typeof(Mem)>();
int offset = pkt->req->getFlags();
if(dataSize != 8 || !offset)
{
Mem = bits(alignedMem.a,
(offset + dataSize) * 8 - 1, offset * 8);
}
else
{
Mem = alignedMem.b << (dataSize - offset) * 8;
Mem |= bits(alignedMem.a, dataSize * 8 - 1, offset * 8);
}
%(code)s; %(code)s;
if(fault == NoFault) if(fault == NoFault)
@ -221,14 +197,7 @@ def template MicroStoreExecute {{
if(fault == NoFault) if(fault == NoFault)
{ {
int offset = EA & (dataSize - 1); fault = write(xc, Mem, EA, 0);
Twin64_t alignedMem;
alignedMem.a = Mem << (offset * 8);
alignedMem.b =
bits(Mem, dataSize * 8 - 1, (dataSize - offset) * 8);
fault = write(xc, alignedMem, EA, 0);
if(fault == NoFault) if(fault == NoFault)
{ {
%(op_wb)s; %(op_wb)s;
@ -255,14 +224,7 @@ def template MicroStoreInitiateAcc {{
if(fault == NoFault) if(fault == NoFault)
{ {
int offset = EA & (dataSize - 1); fault = write(xc, Mem, EA, 0);
Twin64_t alignedMem;
alignedMem.a = Mem << (offset * 8);
alignedMem.b =
bits(Mem, dataSize * 8 - 1, (dataSize - offset) * 8);
fault = write(xc, alignedMem, EA, 0);
if(fault == NoFault) if(fault == NoFault)
{ {
%(op_wb)s; %(op_wb)s;