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AddrRange: Simplify AddrRange params Python hierarchy

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This patch simplifies the Range object hierarchy in preparation for an
address range class that also allows striping (e.g. selecting a few
bits as matching in addition to the range).

To extend the AddrRange class to an AddrRegion, the first step is to
simplify the hierarchy such that we can make it as lean as possible
before adding the new functionality. The only class using Range and
MetaRange is AddrRange, and the three classes are now collapsed into
one.
This commit is contained in:
Andreas Hansson 2012-09-19 06:15:41 -04:00
parent 33c904e0a5
commit fccbf8bb45
9 changed files with 43 additions and 70 deletions
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6
configs/common/FSConfig.py
View file

@ -519,7 +519,9 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
# We assume below that there's at least 1MB of memory. We'll require 2
# just to avoid corner cases.
assert(self.physmem.range.second.getValue() >= 0x200000)
phys_mem_size = sum(map(lambda mem: mem.range.size(),
self.memories.unproxy(self)))
assert(phys_mem_size >= 0x200000)
self.e820_table.entries = \
[
@ -527,7 +529,7 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
X86E820Entry(addr = 0, size = '1MB', range_type = 2),
# Mark the rest as available
X86E820Entry(addr = 0x100000,
size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
size = '%dB' % (phys_mem_size - 0x100000),
range_type = 1)
]

5
configs/ruby/MESI_CMP_directory.py
View file

@ -134,9 +134,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):

5
configs/ruby/MI_example.py
View file

@ -105,9 +105,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):

5
configs/ruby/MOESI_CMP_directory.py
View file

@ -133,9 +133,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):

5
configs/ruby/MOESI_CMP_token.py
View file

@ -156,9 +156,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):

5
configs/ruby/MOESI_hammer.py
View file

@ -131,9 +131,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
#

5
configs/ruby/Network_test.py
View file

@ -106,9 +106,8 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cntrl_count += 1
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):

5
configs/ruby/Ruby.py
View file

@ -188,9 +188,8 @@ def create_system(options, system, piobus = None, dma_ports = []):
total_mem_size.value += dir_cntrl.directory.size.value
dir_cntrl.directory.numa_high_bit = numa_bit
phys_mem_size = 0
for mem in system.memories.unproxy(system):
phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
phys_mem_size = sum(map(lambda mem: mem.range.size(),
system.memories.unproxy(system)))
assert(total_mem_size.value == phys_mem_size)
ruby_profiler = RubyProfiler(ruby_system = ruby,

66
src/python/m5/params.py
View file

@ -549,86 +549,64 @@ class Addr(CheckedInt):
else:
return self.value + other
class AddrRange(ParamValue):
cxx_type = 'Range<Addr>'
class MetaRange(MetaParamValue):
def __init__(cls, name, bases, dict):
super(MetaRange, cls).__init__(name, bases, dict)
if name == 'Range':
return
cls.cxx_type = 'Range< %s >' % cls.type.cxx_type
class Range(ParamValue):
__metaclass__ = MetaRange
type = Int # default; can be overridden in subclasses
def __init__(self, *args, **kwargs):
def handle_kwargs(self, kwargs):
if 'end' in kwargs:
self.second = self.type(kwargs.pop('end'))
self.end = Addr(kwargs.pop('end'))
elif 'size' in kwargs:
self.second = self.first + self.type(kwargs.pop('size')) - 1
self.end = self.start + Addr(kwargs.pop('size')) - 1
else:
raise TypeError, "Either end or size must be specified"
if len(args) == 0:
self.first = self.type(kwargs.pop('start'))
self.start = Addr(kwargs.pop('start'))
handle_kwargs(self, kwargs)
elif len(args) == 1:
if kwargs:
self.first = self.type(args[0])
self.start = Addr(args[0])
handle_kwargs(self, kwargs)
elif isinstance(args[0], Range):
self.first = self.type(args[0].first)
self.second = self.type(args[0].second)
elif isinstance(args[0], (list, tuple)):
self.first = self.type(args[0][0])
self.second = self.type(args[0][1])
self.start = Addr(args[0][0])
self.end = Addr(args[0][1])
else:
self.first = self.type(0)
self.second = self.type(args[0]) - 1
self.start = Addr(0)
self.end = Addr(args[0]) - 1
elif len(args) == 2:
self.first = self.type(args[0])
self.second = self.type(args[1])
self.start = Addr(args[0])
self.end = Addr(args[1])
else:
raise TypeError, "Too many arguments specified"
if kwargs:
raise TypeError, "too many keywords: %s" % kwargs.keys()
raise TypeError, "Too many keywords: %s" % kwargs.keys()
def __str__(self):
return '%s:%s' % (self.first, self.second)
return '%s:%s' % (self.start, self.end)
def size(self):
return long(self.end) - long(self.start) + 1
@classmethod
def cxx_predecls(cls, code):
cls.type.cxx_predecls(code)
Addr.cxx_predecls(code)
code('#include "base/range.hh"')
@classmethod
def swig_predecls(cls, code):
cls.type.swig_predecls(code)
Addr.swig_predecls(code)
code('%import "python/swig/range.i"')
class AddrRange(Range):
type = Addr
def getValue(self):
from m5.internal.range import AddrRange
value = AddrRange()
value.start = long(self.first)
value.end = long(self.second)
return value
class TickRange(Range):
type = Tick
def getValue(self):
from m5.internal.range import TickRange
value = TickRange()
value.start = long(self.first)
value.end = long(self.second)
value.start = long(self.start)
value.end = long(self.end)
return value
# Boolean parameter type. Python doesn't let you subclass bool, since
@ -1643,7 +1621,7 @@ __all__ = ['Param', 'VectorParam',
'MemorySize', 'MemorySize32',
'Latency', 'Frequency', 'Clock',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'TickRange',
'AddrRange',
'MaxAddr', 'MaxTick', 'AllMemory',
'Time',
'NextEthernetAddr', 'NULL',