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configs: A more realistic configuration of an ARM-like processor

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This commit is contained in:
Ronald Dreslinski 2012-01-26 14:53:48 -05:00
parent 53c130bf2f
commit fc7cf40de6
3 changed files with 31 additions and 9 deletions
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29
configs/common/CacheConfig.py
View file

@ -32,11 +32,17 @@
import m5 import m5
from m5.objects import * from m5.objects import *
from Caches import * from Caches import *
from O3_ARM_v7a import *
def config_cache(options, system): def config_cache(options, system):
if options.l2cache: if options.l2cache:
system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc, if options.cpu_type == "arm_detailed":
block_size=options.cacheline_size) system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
else:
system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
system.tol2bus = Bus() system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port system.l2.mem_side = system.membus.port
@ -44,10 +50,21 @@ def config_cache(options, system):
for i in xrange(options.num_cpus): for i in xrange(options.num_cpus):
if options.caches: if options.caches:
icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc, if options.cpu_type == "arm_detailed":
block_size=options.cacheline_size) icache = O3_ARM_v7a_ICache(size = options.l1i_size,
dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc, assoc = options.l1i_assoc,
block_size=options.cacheline_size) block_size=options.cacheline_size)
dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
assoc = options.l1d_assoc,
block_size=options.cacheline_size)
else:
icache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
block_size=options.cacheline_size)
dcache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
block_size=options.cacheline_size)
if buildEnv['TARGET_ISA'] == 'x86': if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache, system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(), PageTableWalkerCache(),

3
configs/common/Options.py
View file

@ -28,7 +28,8 @@
# system options # system options
parser.add_option("--cpu-type", type="choice", default="atomic", parser.add_option("--cpu-type", type="choice", default="atomic",
choices = ["atomic", "timing", "detailed", "inorder"], choices = ["atomic", "timing", "detailed", "inorder",
"arm_detailed"],
help = "type of cpu to run with") help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1) parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true") parser.add_option("--caches", action="store_true")

8
configs/common/Simulation.py
View file

@ -34,6 +34,7 @@ import m5
from m5.defines import buildEnv from m5.defines import buildEnv
from m5.objects import * from m5.objects import *
from m5.util import * from m5.util import *
from O3_ARM_v7a import *
addToPath('../common') addToPath('../common')
@ -42,11 +43,14 @@ def setCPUClass(options):
atomic = False atomic = False
if options.cpu_type == "timing": if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass class TmpClass(TimingSimpleCPU): pass
elif options.cpu_type == "detailed": elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
if not options.caches and not options.ruby: if not options.caches and not options.ruby:
print "O3 CPU must be used with caches" print "O3 CPU must be used with caches"
sys.exit(1) sys.exit(1)
class TmpClass(DerivO3CPU): pass if options.cpu_type == "arm_detailed":
class TmpClass(O3_ARM_v7a_3): pass
else:
class TmpClass(DerivO3CPU): pass
elif options.cpu_type == "inorder": elif options.cpu_type == "inorder":
if not options.caches: if not options.caches:
print "InOrder CPU must be used with caches" print "InOrder CPU must be used with caches"