Backing in more changsets, getting closer to compile
base_cache.cc compiles, continuing on src/SConscript: Add in compilation flags for cache files src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Back in more fixes, now base_cache compiles src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lru.cc: src/mem/packet.cc: src/mem/packet.hh: src/mem/request.hh: Backing in more changsets, getting closer to compile --HG-- extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
This commit is contained in:
parent
ed8564a6b9
commit
fc281d0b64
25 changed files with 225 additions and 118 deletions
|
@ -101,6 +101,31 @@ base_sources = Split('''
|
||||||
mem/physical.cc
|
mem/physical.cc
|
||||||
mem/port.cc
|
mem/port.cc
|
||||||
|
|
||||||
|
mem/cache/base_cache.cc
|
||||||
|
mem/cache/cache.cc
|
||||||
|
mem/cache/cache_builder.cc
|
||||||
|
mem/cache/coherence/coherence_protocol.cc
|
||||||
|
mem/cache/coherence/uni_coherence.cc
|
||||||
|
mem/cache/miss/blocking_buffer.cc
|
||||||
|
mem/cache/miss/miss_queue.cc
|
||||||
|
mem/cache/miss/mshr.cc
|
||||||
|
mem/cache/miss/mshr_queue.cc
|
||||||
|
mem/cache/prefetch/base_prefetcher.cc
|
||||||
|
mem/cache/prefetch/ghb_prefetcher.cc
|
||||||
|
mem/cache/prefetch/prefetcher.cc
|
||||||
|
mem/cache/prefetch/stride_prefetcher.cc
|
||||||
|
mem/cache/prefetch/tagged_prefetcher.cc
|
||||||
|
mem/cache/tags/base_tags.cc
|
||||||
|
mem/cache/tags/cache_tags.cc
|
||||||
|
mem/cache/tags/fa_lru.cc
|
||||||
|
mem/cache/tags/iic/cc
|
||||||
|
mem/cache/tags/lru.cc
|
||||||
|
mem/cache/tags/repl/gen.cc
|
||||||
|
mem/cache/tags/repl/repl.cc
|
||||||
|
mem/cache/tags/split.cc
|
||||||
|
mem/cache/tags/split_lifo.cc
|
||||||
|
mem/cache/tags/split_lru.cc
|
||||||
|
|
||||||
sim/builder.cc
|
sim/builder.cc
|
||||||
sim/debug.cc
|
sim/debug.cc
|
||||||
sim/eventq.cc
|
sim/eventq.cc
|
||||||
|
|
52
src/mem/cache/base_cache.cc
vendored
52
src/mem/cache/base_cache.cc
vendored
|
@ -45,11 +45,11 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
|
||||||
{
|
{
|
||||||
blocked = false;
|
blocked = false;
|
||||||
//Start ports at null if more than one is created we should panic
|
//Start ports at null if more than one is created we should panic
|
||||||
cpuSidePort = NULL;
|
//cpuSidePort = NULL;
|
||||||
memSidePort = NULL;
|
//memSidePort = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool
|
void
|
||||||
BaseCache::CachePort::recvStatusChange(Port::Status status)
|
BaseCache::CachePort::recvStatusChange(Port::Status status)
|
||||||
{
|
{
|
||||||
cache->recvStatusChange(status, isCpuSide);
|
cache->recvStatusChange(status, isCpuSide);
|
||||||
|
@ -121,12 +121,16 @@ BaseCache::getPort(const std::string &if_name)
|
||||||
void
|
void
|
||||||
BaseCache::regStats()
|
BaseCache::regStats()
|
||||||
{
|
{
|
||||||
|
Request temp_req;
|
||||||
|
Packet::Command temp_cmd = Packet::ReadReq;
|
||||||
|
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
|
||||||
|
|
||||||
using namespace Stats;
|
using namespace Stats;
|
||||||
|
|
||||||
// Hit statistics
|
// Hit statistics
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
hits[access_idx]
|
hits[access_idx]
|
||||||
.init(maxThreadsPerCPU)
|
.init(maxThreadsPerCPU)
|
||||||
|
@ -141,20 +145,20 @@ BaseCache::regStats()
|
||||||
.desc("number of demand (read+write) hits")
|
.desc("number of demand (read+write) hits")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
demandHits = hits[Read] + hits[Write];
|
demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
|
||||||
|
|
||||||
overallHits
|
overallHits
|
||||||
.name(name() + ".overall_hits")
|
.name(name() + ".overall_hits")
|
||||||
.desc("number of overall hits")
|
.desc("number of overall hits")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
overallHits = demandHits + hits[Soft_Prefetch] + hits[Hard_Prefetch]
|
overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
|
||||||
+ hits[Writeback];
|
+ hits[Packet::Writeback];
|
||||||
|
|
||||||
// Miss statistics
|
// Miss statistics
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
misses[access_idx]
|
misses[access_idx]
|
||||||
.init(maxThreadsPerCPU)
|
.init(maxThreadsPerCPU)
|
||||||
|
@ -169,20 +173,20 @@ BaseCache::regStats()
|
||||||
.desc("number of demand (read+write) misses")
|
.desc("number of demand (read+write) misses")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
demandMisses = misses[Read] + misses[Write];
|
demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
|
||||||
|
|
||||||
overallMisses
|
overallMisses
|
||||||
.name(name() + ".overall_misses")
|
.name(name() + ".overall_misses")
|
||||||
.desc("number of overall misses")
|
.desc("number of overall misses")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
overallMisses = demandMisses + misses[Soft_Prefetch] +
|
overallMisses = demandMisses + misses[Packet::SoftPFReq] +
|
||||||
misses[Hard_Prefetch] + misses[Writeback];
|
misses[Packet::HardPFReq] + misses[Packet::Writeback];
|
||||||
|
|
||||||
// Miss latency statistics
|
// Miss latency statistics
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
missLatency[access_idx]
|
missLatency[access_idx]
|
||||||
.init(maxThreadsPerCPU)
|
.init(maxThreadsPerCPU)
|
||||||
|
@ -197,20 +201,20 @@ BaseCache::regStats()
|
||||||
.desc("number of demand (read+write) miss cycles")
|
.desc("number of demand (read+write) miss cycles")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
demandMissLatency = missLatency[Read] + missLatency[Write];
|
demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
|
||||||
|
|
||||||
overallMissLatency
|
overallMissLatency
|
||||||
.name(name() + ".overall_miss_latency")
|
.name(name() + ".overall_miss_latency")
|
||||||
.desc("number of overall miss cycles")
|
.desc("number of overall miss cycles")
|
||||||
.flags(total)
|
.flags(total)
|
||||||
;
|
;
|
||||||
overallMissLatency = demandMissLatency + missLatency[Soft_Prefetch] +
|
overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
|
||||||
missLatency[Hard_Prefetch];
|
missLatency[Packet::HardPFReq];
|
||||||
|
|
||||||
// access formulas
|
// access formulas
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
accesses[access_idx]
|
accesses[access_idx]
|
||||||
.name(name() + "." + cstr + "_accesses")
|
.name(name() + "." + cstr + "_accesses")
|
||||||
|
@ -237,8 +241,8 @@ BaseCache::regStats()
|
||||||
|
|
||||||
// miss rate formulas
|
// miss rate formulas
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
missRate[access_idx]
|
missRate[access_idx]
|
||||||
.name(name() + "." + cstr + "_miss_rate")
|
.name(name() + "." + cstr + "_miss_rate")
|
||||||
|
@ -265,8 +269,8 @@ BaseCache::regStats()
|
||||||
|
|
||||||
// miss latency formulas
|
// miss latency formulas
|
||||||
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
|
||||||
Packet::Command cmd = (Packet::CommandEnum)access_idx;
|
Packet::Command cmd = (Packet::Command)access_idx;
|
||||||
const string &cstr = cmd.toString();
|
const string &cstr = temp_pkt.cmdIdxToString(cmd);
|
||||||
|
|
||||||
avgMissLatency[access_idx]
|
avgMissLatency[access_idx]
|
||||||
.name(name() + "." + cstr + "_avg_miss_latency")
|
.name(name() + "." + cstr + "_avg_miss_latency")
|
||||||
|
|
29
src/mem/cache/base_cache.hh
vendored
29
src/mem/cache/base_cache.hh
vendored
|
@ -47,6 +47,7 @@
|
||||||
#include "mem/packet.hh"
|
#include "mem/packet.hh"
|
||||||
#include "mem/port.hh"
|
#include "mem/port.hh"
|
||||||
#include "mem/request.hh"
|
#include "mem/request.hh"
|
||||||
|
#include "sim/eventq.hh"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Reasons for Caches to be Blocked.
|
* Reasons for Caches to be Blocked.
|
||||||
|
@ -82,7 +83,7 @@ class BaseCache : public MemObject
|
||||||
public:
|
public:
|
||||||
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
|
CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
|
||||||
|
|
||||||
private:
|
protected:
|
||||||
virtual bool recvTiming(Packet *pkt);
|
virtual bool recvTiming(Packet *pkt);
|
||||||
|
|
||||||
virtual Tick recvAtomic(Packet *pkt);
|
virtual Tick recvAtomic(Packet *pkt);
|
||||||
|
@ -96,6 +97,7 @@ class BaseCache : public MemObject
|
||||||
|
|
||||||
virtual int deviceBlockSize();
|
virtual int deviceBlockSize();
|
||||||
|
|
||||||
|
public:
|
||||||
void setBlocked();
|
void setBlocked();
|
||||||
|
|
||||||
void clearBlocked();
|
void clearBlocked();
|
||||||
|
@ -110,10 +112,10 @@ class BaseCache : public MemObject
|
||||||
Packet *pkt;
|
Packet *pkt;
|
||||||
CachePort *cachePort;
|
CachePort *cachePort;
|
||||||
|
|
||||||
CacheResponseEvent(Packet *pkt, CachePort *cachePort);
|
CacheEvent(Packet *pkt, CachePort *cachePort);
|
||||||
void process();
|
void process();
|
||||||
const char *description();
|
const char *description();
|
||||||
}
|
};
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
CachePort *cpuSidePort;
|
CachePort *cpuSidePort;
|
||||||
|
@ -124,7 +126,7 @@ class BaseCache : public MemObject
|
||||||
|
|
||||||
private:
|
private:
|
||||||
//To be defined in cache_impl.hh not in base class
|
//To be defined in cache_impl.hh not in base class
|
||||||
virtual bool doTimingAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide);
|
virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide);
|
||||||
virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
|
virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
|
||||||
virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
|
virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
|
||||||
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
|
virtual void recvStatusChange(Port::Status status, bool isCpuSide);
|
||||||
|
@ -275,12 +277,14 @@ class BaseCache : public MemObject
|
||||||
* of this cache.
|
* of this cache.
|
||||||
* @param params The parameter object for this BaseCache.
|
* @param params The parameter object for this BaseCache.
|
||||||
*/
|
*/
|
||||||
BaseCache(const std::string &name, HierParams *hier_params, Params ¶ms)
|
BaseCache(const std::string &name, Params ¶ms)
|
||||||
: BaseMem(name, hier_params, params.hitLatency, params.addrRange),
|
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
|
||||||
blocked(0), blockedSnoop(0), masterRequests(0), slaveRequests(0),
|
slaveRequests(0), topLevelCache(false), blkSize(params.blkSize),
|
||||||
topLevelCache(false), blkSize(params.blkSize),
|
|
||||||
missCount(params.maxMisses)
|
missCount(params.maxMisses)
|
||||||
{
|
{
|
||||||
|
//Start ports at null if more than one is created we should panic
|
||||||
|
cpuSidePort = NULL;
|
||||||
|
memSidePort = NULL;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -453,8 +457,8 @@ class BaseCache : public MemObject
|
||||||
*/
|
*/
|
||||||
void respondToMiss(Packet *pkt, Tick time)
|
void respondToMiss(Packet *pkt, Tick time)
|
||||||
{
|
{
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
missLatency[pkt->cmd.toIndex()][pkt->thread_num] += time - pkt->time;
|
missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
|
||||||
}
|
}
|
||||||
assert("Implement\n" && 0);
|
assert("Implement\n" && 0);
|
||||||
// si->respond(pkt,time);
|
// si->respond(pkt,time);
|
||||||
|
@ -475,6 +479,11 @@ class BaseCache : public MemObject
|
||||||
* to do for a cache.
|
* to do for a cache.
|
||||||
*/
|
*/
|
||||||
void rangeChange() {}
|
void rangeChange() {}
|
||||||
|
|
||||||
|
void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
|
||||||
|
{
|
||||||
|
panic("Unimplimented\n");
|
||||||
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif //__BASE_CACHE_HH__
|
#endif //__BASE_CACHE_HH__
|
||||||
|
|
7
src/mem/cache/cache.hh
vendored
7
src/mem/cache/cache.hh
vendored
|
@ -46,7 +46,6 @@
|
||||||
|
|
||||||
// forward declarations
|
// forward declarations
|
||||||
class Bus;
|
class Bus;
|
||||||
class ExecContext;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* A template-policy based cache. The behavior of the cache can be altered by
|
* A template-policy based cache. The behavior of the cache can be altered by
|
||||||
|
@ -209,11 +208,11 @@ class Cache : public BaseCache
|
||||||
/**
|
/**
|
||||||
* Aquash all requests associated with specified thread.
|
* Aquash all requests associated with specified thread.
|
||||||
* intended for use by I-cache.
|
* intended for use by I-cache.
|
||||||
* @param thread_number The thread to squash.
|
* @param req->getThreadNum()ber The thread to squash.
|
||||||
*/
|
*/
|
||||||
void squash(int thread_number)
|
void squash(int threadNum)
|
||||||
{
|
{
|
||||||
missQueue->squash(thread_number);
|
missQueue->squash(threadNum);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
4
src/mem/cache/cache_blk.hh
vendored
4
src/mem/cache/cache_blk.hh
vendored
|
@ -37,7 +37,6 @@
|
||||||
|
|
||||||
#include "sim/root.hh" // for Tick
|
#include "sim/root.hh" // for Tick
|
||||||
#include "arch/isa_traits.hh" // for Addr
|
#include "arch/isa_traits.hh" // for Addr
|
||||||
#include "cpu/exec_context.hh"
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Cache block status bit assignments
|
* Cache block status bit assignments
|
||||||
|
@ -88,9 +87,6 @@ class CacheBlk
|
||||||
/** Which curTick will this block be accessable */
|
/** Which curTick will this block be accessable */
|
||||||
Tick whenReady;
|
Tick whenReady;
|
||||||
|
|
||||||
/** Save the exec context so that writebacks can use them. */
|
|
||||||
ExecContext *xc;
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* The set this block belongs to.
|
* The set this block belongs to.
|
||||||
* @todo Move this into subclasses when we fix CacheTags to use them.
|
* @todo Move this into subclasses when we fix CacheTags to use them.
|
||||||
|
|
26
src/mem/cache/cache_impl.hh
vendored
26
src/mem/cache/cache_impl.hh
vendored
|
@ -175,7 +175,7 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
|
||||||
//We are determining prefetches on access stream, call prefetcher
|
//We are determining prefetches on access stream, call prefetcher
|
||||||
prefetcher->handleMiss(pkt, curTick);
|
prefetcher->handleMiss(pkt, curTick);
|
||||||
}
|
}
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
|
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
|
||||||
&& !pkt->cmd.isWrite()) {
|
&& !pkt->cmd.isWrite()) {
|
||||||
//Upgrade or Invalidate
|
//Upgrade or Invalidate
|
||||||
|
@ -220,7 +220,7 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
|
||||||
pkt->paddr & ~((Addr)blkSize - 1), pkt->pc);
|
pkt->paddr & ~((Addr)blkSize - 1), pkt->pc);
|
||||||
if (blk) {
|
if (blk) {
|
||||||
// Hit
|
// Hit
|
||||||
hits[pkt->cmd.toIndex()][pkt->thread_num]++;
|
hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
// clear dirty bit if write through
|
// clear dirty bit if write through
|
||||||
if (!pkt->cmd.isNoResponse())
|
if (!pkt->cmd.isNoResponse())
|
||||||
respond(pkt, curTick+lat);
|
respond(pkt, curTick+lat);
|
||||||
|
@ -228,8 +228,8 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
|
||||||
}
|
}
|
||||||
|
|
||||||
// Miss
|
// Miss
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
misses[pkt->cmd.toIndex()][pkt->thread_num]++;
|
misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
/** @todo Move miss count code into BaseCache */
|
/** @todo Move miss count code into BaseCache */
|
||||||
if (missCount) {
|
if (missCount) {
|
||||||
--missCount;
|
--missCount;
|
||||||
|
@ -248,8 +248,8 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
|
||||||
{
|
{
|
||||||
Packet * pkt = missQueue->getPacket();
|
Packet * pkt = missQueue->getPacket();
|
||||||
if (pkt) {
|
if (pkt) {
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
if (pkt->cmd == Hard_Prefetch) misses[Hard_Prefetch][pkt->thread_num]++;
|
if (pkt->cmd == Hard_Prefetch) misses[Hard_Prefetch][pkt->req->getThreadNum()]++;
|
||||||
BlkType *blk = tags->findBlock(pkt);
|
BlkType *blk = tags->findBlock(pkt);
|
||||||
Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
|
Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
|
||||||
(blk)? blk->status : 0);
|
(blk)? blk->status : 0);
|
||||||
|
@ -272,7 +272,7 @@ Cache<TagStore,Buffering,Coherence>::sendResult(MemPktPtr &pkt, bool success)
|
||||||
if (pkt->cmd == Upgrade) {
|
if (pkt->cmd == Upgrade) {
|
||||||
handleResponse(pkt);
|
handleResponse(pkt);
|
||||||
}
|
}
|
||||||
} else if (pkt && !pkt->isUncacheable()) {
|
} else if (pkt && !pkt->req->isUncacheable()) {
|
||||||
missQueue->restoreOrigCmd(pkt);
|
missQueue->restoreOrigCmd(pkt);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -394,7 +394,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
|
||||||
for (int i=0; i<writebacks.size(); i++) {
|
for (int i=0; i<writebacks.size(); i++) {
|
||||||
mshr = writebacks[i];
|
mshr = writebacks[i];
|
||||||
|
|
||||||
if (!mshr->pkt->isUncacheable()) {
|
if (!mshr->pkt->req->isUncacheable()) {
|
||||||
if (pkt->cmd.isRead()) {
|
if (pkt->cmd.isRead()) {
|
||||||
//Only Upgrades don't get here
|
//Only Upgrades don't get here
|
||||||
//Supply the data
|
//Supply the data
|
||||||
|
@ -469,7 +469,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
||||||
{
|
{
|
||||||
MemDebug::cacheProbe(pkt);
|
MemDebug::cacheProbe(pkt);
|
||||||
|
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
|
if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
|
||||||
&& !pkt->cmd.isWrite()) {
|
&& !pkt->cmd.isWrite()) {
|
||||||
//Upgrade or Invalidate, satisfy it, don't forward
|
//Upgrade or Invalidate, satisfy it, don't forward
|
||||||
|
@ -583,7 +583,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
||||||
// Can't handle it, return pktuest unsatisfied.
|
// Can't handle it, return pktuest unsatisfied.
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
// Fetch the cache block to fill
|
// Fetch the cache block to fill
|
||||||
Packet * busPkt = new MemPkt();
|
Packet * busPkt = new MemPkt();
|
||||||
busPkt->paddr = blk_addr;
|
busPkt->paddr = blk_addr;
|
||||||
|
@ -596,7 +596,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
||||||
|
|
||||||
busPkt->req->asid = pkt->req->asid;
|
busPkt->req->asid = pkt->req->asid;
|
||||||
busPkt->xc = pkt->xc;
|
busPkt->xc = pkt->xc;
|
||||||
busPkt->thread_num = pkt->thread_num;
|
busPkt->req->setThreadNum() = pkt->req->getThreadNum();
|
||||||
busPkt->time = curTick;
|
busPkt->time = curTick;
|
||||||
|
|
||||||
lat = mi->sendProbe(busPkt, update);
|
lat = mi->sendProbe(busPkt, update);
|
||||||
|
@ -606,7 +606,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
misses[pkt->cmd.toIndex()][pkt->thread_num]++;
|
misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
|
|
||||||
CacheBlk::State old_state = (blk) ? blk->status : 0;
|
CacheBlk::State old_state = (blk) ? blk->status : 0;
|
||||||
tags->handleFill(blk, busPkt,
|
tags->handleFill(blk, busPkt,
|
||||||
|
@ -631,7 +631,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (update) {
|
if (update) {
|
||||||
hits[pkt->cmd.toIndex()][pkt->thread_num]++;
|
hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
} else if (pkt->cmd.isWrite()) {
|
} else if (pkt->cmd.isWrite()) {
|
||||||
// Still need to change data in all locations.
|
// Still need to change data in all locations.
|
||||||
return mi->sendProbe(pkt, update);
|
return mi->sendProbe(pkt, update);
|
||||||
|
|
|
@ -465,7 +465,7 @@ CacheBlk::State
|
||||||
CoherenceProtocol::getNewState(const Packet * &pkt, CacheBlk::State oldState)
|
CoherenceProtocol::getNewState(const Packet * &pkt, CacheBlk::State oldState)
|
||||||
{
|
{
|
||||||
CacheBlk::State state = oldState & stateMask;
|
CacheBlk::State state = oldState & stateMask;
|
||||||
int cmd_idx = pkt->cmd.toIndex();
|
int cmd_idx = pkt->cmdToIndex();
|
||||||
|
|
||||||
assert(0 <= state && state <= stateMax);
|
assert(0 <= state && state <= stateMax);
|
||||||
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
|
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
|
||||||
|
@ -498,7 +498,7 @@ CoherenceProtocol::handleBusRequest(BaseCache *cache, Packet * &pkt,
|
||||||
}
|
}
|
||||||
|
|
||||||
CacheBlk::State state = blk->status & stateMask;
|
CacheBlk::State state = blk->status & stateMask;
|
||||||
int cmd_idx = pkt->cmd.toIndex();
|
int cmd_idx = pkt->cmdToIndex();
|
||||||
|
|
||||||
assert(0 <= state && state <= stateMax);
|
assert(0 <= state && state <= stateMax);
|
||||||
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
|
assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
|
||||||
|
|
22
src/mem/cache/miss/blocking_buffer.cc
vendored
22
src/mem/cache/miss/blocking_buffer.cc
vendored
|
@ -73,7 +73,7 @@ void
|
||||||
BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
|
BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
|
||||||
{
|
{
|
||||||
Addr blk_addr = pkt->paddr & ~(Addr)(blk_size - 1);
|
Addr blk_addr = pkt->paddr & ~(Addr)(blk_size - 1);
|
||||||
if (pkt->cmd.isWrite() && (pkt->isUncacheable() || !writeAllocate ||
|
if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
|
||||||
pkt->cmd.isNoResponse())) {
|
pkt->cmd.isNoResponse())) {
|
||||||
if (pkt->cmd.isNoResponse()) {
|
if (pkt->cmd.isNoResponse()) {
|
||||||
wb.allocateAsBuffer(pkt);
|
wb.allocateAsBuffer(pkt);
|
||||||
|
@ -93,7 +93,7 @@ BlockingBuffer::handleMiss(Packet * &pkt, int blk_size, Tick time)
|
||||||
} else {
|
} else {
|
||||||
miss.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt);
|
miss.allocate(pkt->cmd, blk_addr, pkt->req->asid, blk_size, pkt);
|
||||||
}
|
}
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
miss.pkt->flags |= CACHE_LINE_FILL;
|
miss.pkt->flags |= CACHE_LINE_FILL;
|
||||||
}
|
}
|
||||||
cache->setBlocked(Blocked_NoMSHRs);
|
cache->setBlocked(Blocked_NoMSHRs);
|
||||||
|
@ -186,12 +186,12 @@ BlockingBuffer::handleResponse(Packet * &pkt, Tick time)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
BlockingBuffer::squash(int thread_number)
|
BlockingBuffer::squash(int req->getThreadNum()ber)
|
||||||
{
|
{
|
||||||
if (miss.threadNum == thread_number) {
|
if (miss.setThreadNum() == req->getThreadNum()ber) {
|
||||||
Packet * target = miss.getTarget();
|
Packet * target = miss.getTarget();
|
||||||
miss.popTarget();
|
miss.popTarget();
|
||||||
assert(target->thread_num == thread_number);
|
assert(target->req->setThreadNum() == req->getThreadNum()ber);
|
||||||
if (target->completionEvent != NULL) {
|
if (target->completionEvent != NULL) {
|
||||||
delete target->completionEvent;
|
delete target->completionEvent;
|
||||||
}
|
}
|
||||||
|
@ -207,7 +207,7 @@ BlockingBuffer::squash(int thread_number)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
|
BlockingBuffer::doWriteback(Addr addr, int asid,
|
||||||
int size, uint8_t *data, bool compressed)
|
int size, uint8_t *data, bool compressed)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
@ -224,18 +224,14 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
|
||||||
* @todo Need to find a way to charge the writeback to the "correct"
|
* @todo Need to find a way to charge the writeback to the "correct"
|
||||||
* thread.
|
* thread.
|
||||||
*/
|
*/
|
||||||
pkt->xc = xc;
|
pkt->req->setThreadNum() = 0;
|
||||||
if (xc)
|
|
||||||
pkt->thread_num = xc->getThreadNum();
|
|
||||||
else
|
|
||||||
pkt->thread_num = 0;
|
|
||||||
|
|
||||||
pkt->cmd = Writeback;
|
pkt->cmd = Writeback;
|
||||||
if (compressed) {
|
if (compressed) {
|
||||||
pkt->flags |= COMPRESSED;
|
pkt->flags |= COMPRESSED;
|
||||||
}
|
}
|
||||||
|
|
||||||
writebacks[pkt->thread_num]++;
|
writebacks[pkt->req->getThreadNum()]++;
|
||||||
|
|
||||||
wb.allocateAsBuffer(pkt);
|
wb.allocateAsBuffer(pkt);
|
||||||
cache->setMasterRequest(Request_WB, curTick);
|
cache->setMasterRequest(Request_WB, curTick);
|
||||||
|
@ -247,7 +243,7 @@ BlockingBuffer::doWriteback(Addr addr, int asid, ExecContext *xc,
|
||||||
void
|
void
|
||||||
BlockingBuffer::doWriteback(Packet * &pkt)
|
BlockingBuffer::doWriteback(Packet * &pkt)
|
||||||
{
|
{
|
||||||
writebacks[pkt->thread_num]++;
|
writebacks[pkt->req->getThreadNum()]++;
|
||||||
|
|
||||||
wb.allocateAsBuffer(pkt);
|
wb.allocateAsBuffer(pkt);
|
||||||
|
|
||||||
|
|
7
src/mem/cache/miss/blocking_buffer.hh
vendored
7
src/mem/cache/miss/blocking_buffer.hh
vendored
|
@ -164,9 +164,9 @@ public:
|
||||||
/**
|
/**
|
||||||
* Removes all outstanding requests for a given thread number. If a request
|
* Removes all outstanding requests for a given thread number. If a request
|
||||||
* has been sent to the bus, this function removes all of its targets.
|
* has been sent to the bus, this function removes all of its targets.
|
||||||
* @param thread_number The thread number of the requests to squash.
|
* @param req->getThreadNum()ber The thread number of the requests to squash.
|
||||||
*/
|
*/
|
||||||
void squash(int thread_number);
|
void squash(int req->getThreadNum()ber);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return the current number of outstanding misses.
|
* Return the current number of outstanding misses.
|
||||||
|
@ -212,12 +212,11 @@ public:
|
||||||
* Perform a writeback of dirty data to the given address.
|
* Perform a writeback of dirty data to the given address.
|
||||||
* @param addr The address to write to.
|
* @param addr The address to write to.
|
||||||
* @param asid The address space id.
|
* @param asid The address space id.
|
||||||
* @param xc The execution context of the address space.
|
|
||||||
* @param size The number of bytes to write.
|
* @param size The number of bytes to write.
|
||||||
* @param data The data to write, can be NULL.
|
* @param data The data to write, can be NULL.
|
||||||
* @param compressed True if the data is compressed.
|
* @param compressed True if the data is compressed.
|
||||||
*/
|
*/
|
||||||
void doWriteback(Addr addr, int asid, ExecContext *xc,
|
void doWriteback(Addr addr, int asid,
|
||||||
int size, uint8_t *data, bool compressed);
|
int size, uint8_t *data, bool compressed);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
36
src/mem/cache/miss/miss_queue.cc
vendored
36
src/mem/cache/miss/miss_queue.cc
vendored
|
@ -347,7 +347,7 @@ MissQueue::allocateMiss(Packet * &pkt, int size, Tick time)
|
||||||
{
|
{
|
||||||
MSHR* mshr = mq.allocate(pkt, size);
|
MSHR* mshr = mq.allocate(pkt, size);
|
||||||
mshr->order = order++;
|
mshr->order = order++;
|
||||||
if (!pkt->isUncacheable() ){//&& !pkt->isNoAllocate()) {
|
if (!pkt->req->isUncacheable() ){//&& !pkt->isNoAllocate()) {
|
||||||
// Mark this as a cache line fill
|
// Mark this as a cache line fill
|
||||||
mshr->pkt->flags |= CACHE_LINE_FILL;
|
mshr->pkt->flags |= CACHE_LINE_FILL;
|
||||||
}
|
}
|
||||||
|
@ -399,13 +399,13 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
|
||||||
int size = blkSize;
|
int size = blkSize;
|
||||||
Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
|
Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
|
||||||
MSHR* mshr = NULL;
|
MSHR* mshr = NULL;
|
||||||
if (!pkt->isUncacheable()) {
|
if (!pkt->req->isUncacheable()) {
|
||||||
mshr = mq.findMatch(blkAddr, pkt->req->asid);
|
mshr = mq.findMatch(blkAddr, pkt->req->asid);
|
||||||
if (mshr) {
|
if (mshr) {
|
||||||
//@todo remove hw_pf here
|
//@todo remove hw_pf here
|
||||||
mshr_hits[pkt->cmd.toIndex()][pkt->thread_num]++;
|
mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
if (mshr->threadNum != pkt->thread_num) {
|
if (mshr->getThreadNum() != pkt->req->getThreadNum()) {
|
||||||
mshr->threadNum = -1;
|
mshr->setThreadNum() = -1;
|
||||||
}
|
}
|
||||||
mq.allocateTarget(mshr, pkt);
|
mq.allocateTarget(mshr, pkt);
|
||||||
if (mshr->pkt->isNoAllocate() && !pkt->isNoAllocate()) {
|
if (mshr->pkt->isNoAllocate() && !pkt->isNoAllocate()) {
|
||||||
|
@ -424,14 +424,14 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
|
||||||
mshr_no_allocate_misses++;
|
mshr_no_allocate_misses++;
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
mshr_misses[pkt->cmd.toIndex()][pkt->thread_num]++;
|
mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
//Count uncacheable accesses
|
//Count uncacheable accesses
|
||||||
mshr_uncacheable[pkt->cmd.toIndex()][pkt->thread_num]++;
|
mshr_uncacheable[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
size = pkt->size;
|
size = pkt->size;
|
||||||
}
|
}
|
||||||
if (pkt->cmd.isWrite() && (pkt->isUncacheable() || !writeAllocate ||
|
if (pkt->cmd.isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
|
||||||
pkt->cmd.isNoResponse())) {
|
pkt->cmd.isNoResponse())) {
|
||||||
/**
|
/**
|
||||||
* @todo Add write merging here.
|
* @todo Add write merging here.
|
||||||
|
@ -489,7 +489,7 @@ MissQueue::getPacket()
|
||||||
pkt = prefetcher->getPacket();
|
pkt = prefetcher->getPacket();
|
||||||
if (pkt) {
|
if (pkt) {
|
||||||
//Update statistic on number of prefetches issued (hwpf_mshr_misses)
|
//Update statistic on number of prefetches issued (hwpf_mshr_misses)
|
||||||
mshr_misses[pkt->cmd.toIndex()][pkt->thread_num]++;
|
mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
|
||||||
//It will request the bus for the future, but should clear that immedieatley
|
//It will request the bus for the future, but should clear that immedieatley
|
||||||
allocateMiss(pkt, pkt->size, curTick);
|
allocateMiss(pkt, pkt->size, curTick);
|
||||||
pkt = mq.getReq();
|
pkt = mq.getReq();
|
||||||
|
@ -582,7 +582,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
|
||||||
BlockedCause cause = NUM_BLOCKED_CAUSES;
|
BlockedCause cause = NUM_BLOCKED_CAUSES;
|
||||||
|
|
||||||
if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
|
if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
|
||||||
mshr_miss_latency[mshr->originalCmd][pkt->thread_num] +=
|
mshr_miss_latency[mshr->originalCmd][pkt->req->getThreadNum()] +=
|
||||||
curTick - pkt->time;
|
curTick - pkt->time;
|
||||||
// targets were handled in the cache tags
|
// targets were handled in the cache tags
|
||||||
if (mshr == noTargetMSHR) {
|
if (mshr == noTargetMSHR) {
|
||||||
|
@ -608,11 +608,11 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (pkt->isUncacheable()) {
|
if (pkt->req->isUncacheable()) {
|
||||||
mshr_uncacheable_lat[pkt->cmd][pkt->thread_num] +=
|
mshr_uncacheable_lat[pkt->cmd][pkt->req->getThreadNum()] +=
|
||||||
curTick - pkt->time;
|
curTick - pkt->time;
|
||||||
}
|
}
|
||||||
if (mshr->hasTargets() && pkt->isUncacheable()) {
|
if (mshr->hasTargets() && pkt->req->isUncacheable()) {
|
||||||
// Should only have 1 target if we had any
|
// Should only have 1 target if we had any
|
||||||
assert(num_targets == 1);
|
assert(num_targets == 1);
|
||||||
Packet * target = mshr->getTarget();
|
Packet * target = mshr->getTarget();
|
||||||
|
@ -660,12 +660,12 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
MissQueue::squash(int thread_number)
|
MissQueue::squash(int req->getThreadNum()ber)
|
||||||
{
|
{
|
||||||
bool unblock = false;
|
bool unblock = false;
|
||||||
BlockedCause cause = NUM_BLOCKED_CAUSES;
|
BlockedCause cause = NUM_BLOCKED_CAUSES;
|
||||||
|
|
||||||
if (noTargetMSHR && noTargetMSHR->threadNum == thread_number) {
|
if (noTargetMSHR && noTargetMSHR->setThreadNum() == req->getThreadNum()ber) {
|
||||||
noTargetMSHR = NULL;
|
noTargetMSHR = NULL;
|
||||||
unblock = true;
|
unblock = true;
|
||||||
cause = Blocked_NoTargets;
|
cause = Blocked_NoTargets;
|
||||||
|
@ -674,7 +674,7 @@ MissQueue::squash(int thread_number)
|
||||||
unblock = true;
|
unblock = true;
|
||||||
cause = Blocked_NoMSHRs;
|
cause = Blocked_NoMSHRs;
|
||||||
}
|
}
|
||||||
mq.squash(thread_number);
|
mq.squash(req->getThreadNum()ber);
|
||||||
if (!mq.havePending()) {
|
if (!mq.havePending()) {
|
||||||
cache->clearMasterRequest(Request_MSHR);
|
cache->clearMasterRequest(Request_MSHR);
|
||||||
}
|
}
|
||||||
|
@ -704,7 +704,7 @@ MissQueue::doWriteback(Addr addr, int asid,
|
||||||
Packet * pkt = buildWritebackReq(addr, asid, size, data,
|
Packet * pkt = buildWritebackReq(addr, asid, size, data,
|
||||||
compressed);
|
compressed);
|
||||||
|
|
||||||
writebacks[pkt->thread_num]++;
|
writebacks[pkt->req->getThreadNum()]++;
|
||||||
|
|
||||||
allocateWrite(pkt, 0, curTick);
|
allocateWrite(pkt, 0, curTick);
|
||||||
}
|
}
|
||||||
|
@ -713,7 +713,7 @@ MissQueue::doWriteback(Addr addr, int asid,
|
||||||
void
|
void
|
||||||
MissQueue::doWriteback(Packet * &pkt)
|
MissQueue::doWriteback(Packet * &pkt)
|
||||||
{
|
{
|
||||||
writebacks[pkt->thread_num]++;
|
writebacks[pkt->req->getThreadNum()]++;
|
||||||
allocateWrite(pkt, 0, curTick);
|
allocateWrite(pkt, 0, curTick);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
4
src/mem/cache/miss/miss_queue.hh
vendored
4
src/mem/cache/miss/miss_queue.hh
vendored
|
@ -268,9 +268,9 @@ class MissQueue
|
||||||
/**
|
/**
|
||||||
* Removes all outstanding requests for a given thread number. If a request
|
* Removes all outstanding requests for a given thread number. If a request
|
||||||
* has been sent to the bus, this function removes all of its targets.
|
* has been sent to the bus, this function removes all of its targets.
|
||||||
* @param thread_number The thread number of the requests to squash.
|
* @param req->getThreadNum()ber The thread number of the requests to squash.
|
||||||
*/
|
*/
|
||||||
void squash(int thread_number);
|
void squash(int req->getThreadNum()ber);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Return the current number of outstanding misses.
|
* Return the current number of outstanding misses.
|
||||||
|
|
11
src/mem/cache/miss/mshr.cc
vendored
11
src/mem/cache/miss/mshr.cc
vendored
|
@ -50,7 +50,7 @@ MSHR::MSHR()
|
||||||
{
|
{
|
||||||
inService = false;
|
inService = false;
|
||||||
ntargets = 0;
|
ntargets = 0;
|
||||||
threadNum = -1;
|
setThreadNum() = -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -68,7 +68,7 @@ MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
|
||||||
pkt->data = new uint8_t[size];
|
pkt->data = new uint8_t[size];
|
||||||
pkt->senderState = this;
|
pkt->senderState = this;
|
||||||
//Set the time here for latency calculations
|
//Set the time here for latency calculations
|
||||||
//pkt->time = curTick;
|
pkt->time = curTick;
|
||||||
|
|
||||||
if (target) {
|
if (target) {
|
||||||
pkt->req = target->req;
|
pkt->req = target->req;
|
||||||
|
@ -85,7 +85,7 @@ MSHR::allocateAsBuffer(Packet * &target)
|
||||||
{
|
{
|
||||||
addr = target->paddr;
|
addr = target->paddr;
|
||||||
asid = target->req->asid;
|
asid = target->req->asid;
|
||||||
threadNum = target->thread_num;
|
setThreadNum() = target->req->getThreadNum();
|
||||||
pkt = new Packet();
|
pkt = new Packet();
|
||||||
pkt->addr = target->addr;
|
pkt->addr = target->addr;
|
||||||
pkt->dest = target->dest;
|
pkt->dest = target->dest;
|
||||||
|
@ -94,6 +94,7 @@ MSHR::allocateAsBuffer(Packet * &target)
|
||||||
pkt->req = target->req;
|
pkt->req = target->req;
|
||||||
pkt->data = new uint8_t[target->size];
|
pkt->data = new uint8_t[target->size];
|
||||||
pkt->senderState = this;
|
pkt->senderState = this;
|
||||||
|
pkt->time = curTick;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
|
@ -161,14 +162,14 @@ MSHR::dump()
|
||||||
"inService: %d thread: %d\n"
|
"inService: %d thread: %d\n"
|
||||||
"Addr: %x asid: %d ntargets %d\n"
|
"Addr: %x asid: %d ntargets %d\n"
|
||||||
"Targets:\n",
|
"Targets:\n",
|
||||||
inService, threadNum, addr, asid, ntargets);
|
inService, getThreadNum(), addr, asid, ntargets);
|
||||||
|
|
||||||
TargetListIterator tar_it = targets.begin();
|
TargetListIterator tar_it = targets.begin();
|
||||||
for (int i = 0; i < ntargets; i++) {
|
for (int i = 0; i < ntargets; i++) {
|
||||||
assert(tar_it != targets.end());
|
assert(tar_it != targets.end());
|
||||||
|
|
||||||
ccprintf(cerr, "\t%d: Addr: %x cmd: %d\n",
|
ccprintf(cerr, "\t%d: Addr: %x cmd: %d\n",
|
||||||
i, (*tar_it)->paddr, (*tar_it)->cmd.toIndex());
|
i, (*tar_it)->paddr, (*tar_it)->cmdToIndex());
|
||||||
|
|
||||||
tar_it++;
|
tar_it++;
|
||||||
}
|
}
|
||||||
|
|
2
src/mem/cache/miss/mshr.hh
vendored
2
src/mem/cache/miss/mshr.hh
vendored
|
@ -66,7 +66,7 @@ class MSHR {
|
||||||
/** True if the request has been sent to the bus. */
|
/** True if the request has been sent to the bus. */
|
||||||
bool inService;
|
bool inService;
|
||||||
/** Thread number of the miss. */
|
/** Thread number of the miss. */
|
||||||
int threadNum;
|
int getThreadNum();
|
||||||
/** The request that is forwarded to the next level of the hierarchy. */
|
/** The request that is forwarded to the next level of the hierarchy. */
|
||||||
Packet * pkt;
|
Packet * pkt;
|
||||||
/** The number of currently allocated targets. */
|
/** The number of currently allocated targets. */
|
||||||
|
|
6
src/mem/cache/miss/mshr_queue.cc
vendored
6
src/mem/cache/miss/mshr_queue.cc
vendored
|
@ -237,18 +237,18 @@ MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd)
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
MSHRQueue::squash(int thread_number)
|
MSHRQueue::squash(int req->getThreadNum()ber)
|
||||||
{
|
{
|
||||||
MSHR::Iterator i = allocatedList.begin();
|
MSHR::Iterator i = allocatedList.begin();
|
||||||
MSHR::Iterator end = allocatedList.end();
|
MSHR::Iterator end = allocatedList.end();
|
||||||
for (; i != end;) {
|
for (; i != end;) {
|
||||||
MSHR *mshr = *i;
|
MSHR *mshr = *i;
|
||||||
if (mshr->threadNum == thread_number) {
|
if (mshr->setThreadNum() == req->getThreadNum()ber) {
|
||||||
while (mshr->hasTargets()) {
|
while (mshr->hasTargets()) {
|
||||||
Packet * target = mshr->getTarget();
|
Packet * target = mshr->getTarget();
|
||||||
mshr->popTarget();
|
mshr->popTarget();
|
||||||
|
|
||||||
assert(target->thread_num == thread_number);
|
assert(target->req->setThreadNum() == req->getThreadNum()ber);
|
||||||
if (target->completionEvent != NULL) {
|
if (target->completionEvent != NULL) {
|
||||||
delete target->completionEvent;
|
delete target->completionEvent;
|
||||||
}
|
}
|
||||||
|
|
4
src/mem/cache/miss/mshr_queue.hh
vendored
4
src/mem/cache/miss/mshr_queue.hh
vendored
|
@ -190,9 +190,9 @@ class MSHRQueue {
|
||||||
/**
|
/**
|
||||||
* Squash outstanding requests with the given thread number. If a request
|
* Squash outstanding requests with the given thread number. If a request
|
||||||
* is in service, just squashes the targets.
|
* is in service, just squashes the targets.
|
||||||
* @param thread_number The thread to squash.
|
* @param req->getThreadNum()ber The thread to squash.
|
||||||
*/
|
*/
|
||||||
void squash(int thread_number);
|
void squash(int req->getThreadNum()ber);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Returns true if the pending list is not empty.
|
* Returns true if the pending list is not empty.
|
||||||
|
|
4
src/mem/cache/prefetch/base_prefetcher.cc
vendored
4
src/mem/cache/prefetch/base_prefetcher.cc
vendored
|
@ -132,7 +132,7 @@ BasePrefetcher::getPacket()
|
||||||
void
|
void
|
||||||
BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
|
BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
|
||||||
{
|
{
|
||||||
if (!pkt->isUncacheable() && !(pkt->isInstRead() && only_data))
|
if (!pkt->req->isUncacheable() && !(pkt->isInstRead() && only_data))
|
||||||
{
|
{
|
||||||
//Calculate the blk address
|
//Calculate the blk address
|
||||||
Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
|
Addr blkAddr = pkt->paddr & ~(Addr)(blkSize-1);
|
||||||
|
@ -185,7 +185,7 @@ BasePrefetcher::handleMiss(Packet * &pkt, Tick time)
|
||||||
prefetch->xc = pkt->xc;
|
prefetch->xc = pkt->xc;
|
||||||
prefetch->data = new uint8_t[blkSize];
|
prefetch->data = new uint8_t[blkSize];
|
||||||
prefetch->req->asid = pkt->req->asid;
|
prefetch->req->asid = pkt->req->asid;
|
||||||
prefetch->thread_num = pkt->thread_num;
|
prefetch->req->setThreadNum() = pkt->req->getThreadNum();
|
||||||
prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
|
prefetch->time = time + (*delay); //@todo ADD LATENCY HERE
|
||||||
//... initialize
|
//... initialize
|
||||||
|
|
||||||
|
|
4
src/mem/cache/tags/fa_lru.cc
vendored
4
src/mem/cache/tags/fa_lru.cc
vendored
|
@ -264,8 +264,8 @@ FALRU::findReplacement(Packet * &pkt, PacketList* &writebacks,
|
||||||
tagHash.erase(blk->tag);
|
tagHash.erase(blk->tag);
|
||||||
tagHash[blkAlign(pkt->paddr)] = blk;
|
tagHash[blkAlign(pkt->paddr)] = blk;
|
||||||
if (blk->isValid()) {
|
if (blk->isValid()) {
|
||||||
int thread_num = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
int req->setThreadNum() = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
||||||
replacements[thread_num]++;
|
replacements[req->getThreadNum()]++;
|
||||||
} else {
|
} else {
|
||||||
tagsInUse++;
|
tagsInUse++;
|
||||||
blk->isTouched = true;
|
blk->isTouched = true;
|
||||||
|
|
4
src/mem/cache/tags/iic.cc
vendored
4
src/mem/cache/tags/iic.cc
vendored
|
@ -418,8 +418,8 @@ IIC::freeReplacementBlock(PacketList* & writebacks)
|
||||||
tag_ptr->isModified() ? "writeback" : "clean");
|
tag_ptr->isModified() ? "writeback" : "clean");
|
||||||
/* write back replaced block data */
|
/* write back replaced block data */
|
||||||
if (tag_ptr && (tag_ptr->isValid())) {
|
if (tag_ptr && (tag_ptr->isValid())) {
|
||||||
int thread_num = (tag_ptr->xc) ? tag_ptr->xc->getThreadNum() : 0;
|
int req->setThreadNum() = (tag_ptr->xc) ? tag_ptr->xc->getThreadNum() : 0;
|
||||||
replacements[thread_num]++;
|
replacements[req->getThreadNum()]++;
|
||||||
totalRefs += tag_ptr->refCount;
|
totalRefs += tag_ptr->refCount;
|
||||||
++sampledRefs;
|
++sampledRefs;
|
||||||
tag_ptr->refCount = 0;
|
tag_ptr->refCount = 0;
|
||||||
|
|
4
src/mem/cache/tags/lru.cc
vendored
4
src/mem/cache/tags/lru.cc
vendored
|
@ -225,8 +225,8 @@ LRU::findReplacement(Packet * &pkt, PacketList* &writebacks,
|
||||||
LRUBlk *blk = sets[set].blks[assoc-1];
|
LRUBlk *blk = sets[set].blks[assoc-1];
|
||||||
sets[set].moveToHead(blk);
|
sets[set].moveToHead(blk);
|
||||||
if (blk->isValid()) {
|
if (blk->isValid()) {
|
||||||
int thread_num = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
int req->setThreadNum() = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
||||||
replacements[thread_num]++;
|
replacements[req->getThreadNum()]++;
|
||||||
totalRefs += blk->refCount;
|
totalRefs += blk->refCount;
|
||||||
++sampledRefs;
|
++sampledRefs;
|
||||||
blk->refCount = 0;
|
blk->refCount = 0;
|
||||||
|
|
4
src/mem/cache/tags/split_lifo.cc
vendored
4
src/mem/cache/tags/split_lifo.cc
vendored
|
@ -317,8 +317,8 @@ SplitLIFO::findReplacement(Packet * &pkt, PacketList* &writebacks,
|
||||||
DPRINTF(Split, "just assigned %#x addr into LIFO, replacing %#x status %#x\n",
|
DPRINTF(Split, "just assigned %#x addr into LIFO, replacing %#x status %#x\n",
|
||||||
pkt->paddr, regenerateBlkAddr(blk->tag, set), blk->status);
|
pkt->paddr, regenerateBlkAddr(blk->tag, set), blk->status);
|
||||||
if (blk->isValid()) {
|
if (blk->isValid()) {
|
||||||
int thread_num = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
int req->setThreadNum() = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
||||||
replacements[thread_num]++;
|
replacements[req->getThreadNum()]++;
|
||||||
totalRefs += blk->refCount;
|
totalRefs += blk->refCount;
|
||||||
++sampledRefs;
|
++sampledRefs;
|
||||||
blk->refCount = 0;
|
blk->refCount = 0;
|
||||||
|
|
4
src/mem/cache/tags/split_lru.cc
vendored
4
src/mem/cache/tags/split_lru.cc
vendored
|
@ -244,8 +244,8 @@ SplitLRU::findReplacement(Packet * &pkt, PacketList* &writebacks,
|
||||||
SplitBlk *blk = sets[set].blks[assoc-1];
|
SplitBlk *blk = sets[set].blks[assoc-1];
|
||||||
sets[set].moveToHead(blk);
|
sets[set].moveToHead(blk);
|
||||||
if (blk->isValid()) {
|
if (blk->isValid()) {
|
||||||
int thread_num = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
int req->setThreadNum() = (blk->xc) ? blk->xc->getThreadNum() : 0;
|
||||||
replacements[thread_num]++;
|
replacements[req->getThreadNum()]++;
|
||||||
totalRefs += blk->refCount;
|
totalRefs += blk->refCount;
|
||||||
++sampledRefs;
|
++sampledRefs;
|
||||||
blk->refCount = 0;
|
blk->refCount = 0;
|
||||||
|
|
42
src/mem/config/cache.hh
Normal file
42
src/mem/config/cache.hh
Normal file
|
@ -0,0 +1,42 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Nathan Binkert
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file
|
||||||
|
* Central location to configure which cache types we want to build
|
||||||
|
* into the simulator. In the future, this should probably be
|
||||||
|
* autogenerated by some sort of configuration script.
|
||||||
|
*/
|
||||||
|
#define USE_CACHE_LRU 1
|
||||||
|
#define USE_CACHE_FALRU 1
|
||||||
|
// #define USE_CACHE_SPLIT 1
|
||||||
|
// #define USE_CACHE_SPLIT_LIFO 1
|
||||||
|
#define USE_CACHE_IIC 1
|
||||||
|
|
|
@ -57,6 +57,19 @@ Packet::cmdString() const
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
const std::string &
|
||||||
|
Packet::cmdIdxToString(Packet::Command idx)
|
||||||
|
{
|
||||||
|
switch (idx) {
|
||||||
|
case ReadReq: return ReadReqString;
|
||||||
|
case WriteReq: return WriteReqString;
|
||||||
|
case WriteReqNoAck: return WriteReqNoAckString;
|
||||||
|
case ReadResp: return ReadRespString;
|
||||||
|
case WriteResp: return WriteRespString;
|
||||||
|
default: return OtherCmdString;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/** delete the data pointed to in the data pointer. Ok to call to matter how
|
/** delete the data pointed to in the data pointer. Ok to call to matter how
|
||||||
* data was allocted. */
|
* data was allocted. */
|
||||||
void
|
void
|
||||||
|
|
|
@ -46,6 +46,10 @@ struct Packet;
|
||||||
typedef Packet* PacketPtr;
|
typedef Packet* PacketPtr;
|
||||||
typedef uint8_t* PacketDataPtr;
|
typedef uint8_t* PacketDataPtr;
|
||||||
|
|
||||||
|
//For statistics we need max number of commands, hard code it at
|
||||||
|
//20 for now. @todo fix later
|
||||||
|
#define NUM_MEM_CMDS 1 << 9
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* A Packet is used to encapsulate a transfer between two objects in
|
* A Packet is used to encapsulate a transfer between two objects in
|
||||||
* the memory system (e.g., the L1 and L2 cache). (In contrast, a
|
* the memory system (e.g., the L1 and L2 cache). (In contrast, a
|
||||||
|
@ -102,6 +106,9 @@ class Packet
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
|
||||||
|
/** Used to calculate latencies for each packet.*/
|
||||||
|
Tick time;
|
||||||
|
|
||||||
/** The special destination address indicating that the packet
|
/** The special destination address indicating that the packet
|
||||||
* should be routed based on its address. */
|
* should be routed based on its address. */
|
||||||
static const short Broadcast = -1;
|
static const short Broadcast = -1;
|
||||||
|
@ -149,6 +156,8 @@ class Packet
|
||||||
IsRequest = 1 << 4,
|
IsRequest = 1 << 4,
|
||||||
IsResponse = 1 << 5,
|
IsResponse = 1 << 5,
|
||||||
NeedsResponse = 1 << 6,
|
NeedsResponse = 1 << 6,
|
||||||
|
IsSWPrefetch = 1 << 7,
|
||||||
|
IsHWPrefetch = 1 << 8
|
||||||
};
|
};
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
@ -159,13 +168,24 @@ class Packet
|
||||||
WriteReq = IsWrite | IsRequest | NeedsResponse,
|
WriteReq = IsWrite | IsRequest | NeedsResponse,
|
||||||
WriteReqNoAck = IsWrite | IsRequest,
|
WriteReqNoAck = IsWrite | IsRequest,
|
||||||
ReadResp = IsRead | IsResponse,
|
ReadResp = IsRead | IsResponse,
|
||||||
WriteResp = IsWrite | IsResponse
|
WriteResp = IsWrite | IsResponse,
|
||||||
|
Writeback = IsWrite | IsRequest,
|
||||||
|
SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse,
|
||||||
|
HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse,
|
||||||
|
SoftPFResp = IsRead | IsRequest | IsSWPrefetch | IsResponse,
|
||||||
|
HardPFResp = IsRead | IsRequest | IsHWPrefetch | IsResponse
|
||||||
};
|
};
|
||||||
|
|
||||||
/** Return the string name of the cmd field (for debugging and
|
/** Return the string name of the cmd field (for debugging and
|
||||||
* tracing). */
|
* tracing). */
|
||||||
const std::string &cmdString() const;
|
const std::string &cmdString() const;
|
||||||
|
|
||||||
|
/** Reutrn the string to a cmd given by idx. */
|
||||||
|
const std::string &cmdIdxToString(Command idx);
|
||||||
|
|
||||||
|
/** Return the index of this command. */
|
||||||
|
inline int cmdToIndex() const { return (int) cmd; }
|
||||||
|
|
||||||
/** The command field of the packet. */
|
/** The command field of the packet. */
|
||||||
Command cmd;
|
Command cmd;
|
||||||
|
|
||||||
|
|
|
@ -224,6 +224,9 @@ class Request
|
||||||
/** Accessor function for pc.*/
|
/** Accessor function for pc.*/
|
||||||
Addr getPC() { assert(validPC); return pc; }
|
Addr getPC() { assert(validPC); return pc; }
|
||||||
|
|
||||||
|
/** Accessor Function to Check Cacheability. */
|
||||||
|
bool isUncacheable() { return getFlags() & UNCACHEABLE; }
|
||||||
|
|
||||||
friend class Packet;
|
friend class Packet;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue