arm, config: Fixups for the example big.LITTLE(tm) configuration
This patch refactors the configuration file to use a more object-oriented design. Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
This commit is contained in:
Gabor Dozsa
parent
443da2c030
commit
fb349aa984
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@ -42,6 +42,7 @@ import m5
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from m5.objects import *
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m5.util.addToPath('../../common')
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from Caches import *
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import CpuConfig
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class L1I(L1_ICache):
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hit_latency = 1
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@ -98,33 +99,104 @@ class MemBus(SystemXBar):
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default = Self.badaddr_responder.pio
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class CpuCluster(SubSystem):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage,
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cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
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super(CpuCluster, self).__init__()
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self._cpu_type = cpu_type
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self._l1i_type = l1i_type
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self._l1d_type = l1d_type
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self._wcache_type = wcache_type
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self._l2_type = l2_type
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assert num_cpus > 0
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
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clk_domain=self.clk_domain)
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for idx in range(num_cpus) ]
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for cpu in self.cpus:
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.socket_id = system.numCpuClusters()
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system.addCpuCluster(self, num_cpus)
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def requireCaches(self):
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return self._cpu_type.require_caches()
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def memoryMode(self):
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return self._cpu_type.memory_mode()
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def addL1(self):
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for cpu in self.cpus:
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l1i = None if self._l1i_type is None else self._l1i_type()
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l1d = None if self._l1d_type is None else self._l1d_type()
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iwc = None if self._wcache_type is None else self._wcache_type()
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dwc = None if self._wcache_type is None else self._wcache_type()
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cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
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def addL2(self, clk_domain):
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if self._l2_type is None:
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return
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self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
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self.l2 = self._l2_type()
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for cpu in self.cpus:
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cpu.connectAllPorts(self.toL2Bus)
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self.toL2Bus.master = self.l2.cpu_side
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def connectMemSide(self, bus):
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bus.slave
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try:
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self.l2.mem_side = bus.slave
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except AttributeError:
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for cpu in self.cpus:
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cpu.connectAllPorts(bus)
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class AtomicCluster(CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
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super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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def addL1(self):
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pass
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class SimpleSystem(LinuxArmSystem):
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cache_line_size = 64
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voltage_domain = VoltageDomain(voltage="1.0V")
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clk_domain = SrcClockDomain(clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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def __init__(self, **kwargs):
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super(SimpleSystem, self).__init__(**kwargs)
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realview = VExpress_GEM5_V1()
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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self.clk_domain = SrcClockDomain(clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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gic_cpu_addr = realview.gic.cpu_addr
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flags_addr = realview.realview_io.pio_addr + 0x30
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self.realview = VExpress_GEM5_V1()
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membus = MemBus()
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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intrctrl = IntrControl()
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terminal = Terminal()
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vncserver = VncServer()
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self.membus = MemBus()
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iobus = IOXBar()
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# CPUs->PIO
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iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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_pci_devices = 0
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_clusters = []
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_cpus = []
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self.iobus = IOXBar()
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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self.dmabridge = Bridge(delay='50ns',
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ranges=self.realview._mem_regions)
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self._pci_devices = 0
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self._clusters = []
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self._num_cpus = 0
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def attach_pci(self, dev):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
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@ -142,3 +214,42 @@ class SimpleSystem(LinuxArmSystem):
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.slave
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def numCpuClusters(self):
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return len(self._clusters)
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def addCpuCluster(self, cpu_cluster, num_cpus):
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assert cpu_cluster not in self._clusters
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assert num_cpus > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += num_cpus
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def numCpus(self):
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return self._num_cpus
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def addCaches(self, need_caches, last_cache_level):
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if not need_caches:
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(self.membus)
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return
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cluster_mem_bus = self.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in self._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in self._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(self._clusters,
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key=lambda c: c.clk_domain.clock[0])
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self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
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self.toL3Bus = L2XBar(width=64)
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self.toL3Bus.master = self.l3.cpu_side
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self.l3.mem_side = self.membus.slave
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cluster_mem_bus = self.toL3Bus
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# connect each cluster to the memory hierarchy
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for cluster in self._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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@ -60,10 +60,27 @@ default_rcs = 'bootscript.rcS'
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default_mem_size= "2GB"
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def createSystem(kernel, mem_mode, bootscript, disks=[]):
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class BigCluster(devices.CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock,
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cpu_voltage="1.0V"):
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cpu_config = [ CpuConfig.get("arm_detailed"), devices.L1I, devices.L1D,
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devices.WalkCache, devices.L2 ]
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super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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class LittleCluster(devices.CpuCluster):
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def __init__(self, system, num_cpus, cpu_clock,
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cpu_voltage="1.0V"):
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cpu_config = [ CpuConfig.get("minor"), devices.L1I, devices.L1D,
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devices.WalkCache, devices.L2 ]
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super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
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cpu_voltage, *cpu_config)
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def createSystem(kernel, bootscript, disks=[]):
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sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
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readfile=bootscript,
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mem_mode=mem_mode,
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machine_type="DTOnly")
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mem_region = sys.realview._mem_regions[0]
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@ -91,90 +108,6 @@ def createSystem(kernel, mem_mode, bootscript, disks=[]):
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return sys
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class CpuCluster(SubSystem):
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def addCPUs(self, cpu_config, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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try:
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self._cluster_id
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m5.util.panic("CpuCluster.addCPUs() must be called exactly once")
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except AttributeError:
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pass
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assert num_cpus > 0
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system = self._parent
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self._cluster_id = len(system._clusters)
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system._clusters.append(self)
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self._config = cpu_config
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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cpu_class = cpu_config['cpu']
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self.cpus = [ cpu_class(cpu_id=len(system._cpus) + idx,
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clk_domain=self.clk_domain)
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for idx in range(num_cpus) ]
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for cpu in self.cpus:
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.socket_id = self._cluster_id
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system._cpus.append(cpu)
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def createCache(self, key):
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try:
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return self._config[key]()
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except KeyError:
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return None
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def addL1(self):
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self._cluster_id
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for cpu in self.cpus:
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l1i = self.createCache('l1i')
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l1d = self.createCache('l1d')
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iwc = self.createCache('wcache')
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dwc = self.createCache('wcache')
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cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
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def addL2(self, clk_domain):
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self._cluster_id
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self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
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#self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain,
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#snoop_filter=NULL)
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self.l2 = self._config['l2']()
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for cpu in self.cpus:
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cpu.connectAllPorts(self.toL2Bus)
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self.toL2Bus.master = self.l2.cpu_side
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def connectMemSide(self, bus):
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self._cluster_id
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bus.slave
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try:
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self.l2.mem_side = bus.slave
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except AttributeError:
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for cpu in self.cpus:
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cpu.connectAllPorts(bus)
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def addCaches(system, last_cache_level):
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cluster_mem_bus = system.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in system._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in system._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(system._clusters,
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key=lambda c: c.clk_domain.clock[0])
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system.l3 = devices.L3(clk_domain=max_clock_cluster.clk_domain)
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system.toL3Bus = L2XBar(width=64)
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system.toL3Bus.master = system.l3.cpu_side
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system.l3.mem_side = system.membus.slave
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cluster_mem_bus = system.toL3Bus
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return cluster_mem_bus
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def main():
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parser = argparse.ArgumentParser(
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description="Generic ARM big.LITTLE configuration")
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@ -210,24 +143,6 @@ def main():
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options = parser.parse_args()
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if options.atomic:
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cpu_config = { 'cpu' : AtomicSimpleCPU }
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big_cpu_config, little_cpu_config = cpu_config, cpu_config
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else:
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big_cpu_config = { 'cpu' : CpuConfig.get("arm_detailed"),
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'l1i' : devices.L1I,
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'l1d' : devices.L1D,
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'wcache' : devices.WalkCache,
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'l2' : devices.L2 }
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little_cpu_config = { 'cpu' : MinorCPU,
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'l1i' : devices.L1I,
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'l1d' : devices.L1D,
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'wcache' : devices.WalkCache,
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'l2' : devices.L2 }
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big_cpu_class = big_cpu_config['cpu']
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little_cpu_class = little_cpu_config['cpu']
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kernel_cmd = [
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"earlyprintk=pl011,0x1c090000",
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"console=ttyAMA0",
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@ -243,41 +158,49 @@ def main():
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root = Root(full_system=True)
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assert big_cpu_class.memory_mode() == little_cpu_class.memory_mode()
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disks = default_disk if len(options.disk) == 0 else options.disk
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system = createSystem(options.kernel, big_cpu_class.memory_mode(),
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options.bootscript, disks=disks)
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system = createSystem(options.kernel, options.bootscript, disks=disks)
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root.system = system
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system.boot_osflags = " ".join(kernel_cmd)
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AtomicCluster = devices.AtomicCluster
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if options.big_cpus + options.little_cpus == 0:
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m5.util.panic("Empty CPU clusters")
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# big cluster
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if options.big_cpus > 0:
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system.bigCluster = CpuCluster()
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system.bigCluster.addCPUs(big_cpu_config, options.big_cpus,
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options.big_cpu_clock)
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# LITTLE cluster
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if options.atomic:
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system.bigCluster = AtomicCluster(system, options.big_cpus,
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options.big_cpu_clock)
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else:
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system.bigCluster = BigCluster(system, options.big_cpus,
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options.big_cpu_clock)
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mem_mode = system.bigCluster.memoryMode()
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# little cluster
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if options.little_cpus > 0:
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system.littleCluster = CpuCluster()
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system.littleCluster.addCPUs(little_cpu_config, options.little_cpus,
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options.little_cpu_clock)
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if options.atomic:
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system.littleCluster = AtomicCluster(system, options.little_cpus,
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options.little_cpu_clock)
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# add caches
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if options.caches:
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cluster_mem_bus = addCaches(system, options.last_cache_level)
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else:
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if big_cpu_class.require_caches():
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m5.util.panic("CPU model %s requires caches" % str(big_cpu_class))
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if little_cpu_class.require_caches():
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m5.util.panic("CPU model %s requires caches" %
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str(little_cpu_class))
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cluster_mem_bus = system.membus
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else:
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system.littleCluster = LittleCluster(system, options.little_cpus,
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options.little_cpu_clock)
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mem_mode = system.littleCluster.memoryMode()
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# connect each cluster to the memory hierarchy
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for cluster in system._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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if options.big_cpus > 0 and options.little_cpus > 0:
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if system.bigCluster.memoryMode() != system.littleCluster.memoryMode():
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m5.util.panic("Memory mode missmatch among CPU clusters")
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system.mem_mode = mem_mode
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# create caches
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system.addCaches(options.caches, options.last_cache_level)
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if not options.caches:
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if options.big_cpus > 0 and system.bigCluster.requireCaches():
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m5.util.panic("Big CPU model requires caches")
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if options.little_cpus > 0 and system.littleCluster.requireCaches():
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m5.util.panic("Little CPU model requires caches")
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# Linux device tree
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system.dtb_filename = SysPaths.binary(options.dtb)
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