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ruby: fixed dma mi example to work with multiple dma ports

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This commit is contained in:
Brad Beckmann 2009-11-18 13:55:58 -08:00
parent f54790977b
commit faf1d97f24
4 changed files with 18 additions and 11 deletions
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24
src/mem/protocol/MI_example-dir.sm
View file

@ -1,8 +1,6 @@
machine(Directory, "Directory protocol")
: int directory_latency,
int dma_select_low_bit,
int dma_select_num_bits
: int directory_latency
{
MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
@ -74,6 +72,7 @@ machine(Directory, "Directory protocol")
State TBEState, desc="Transient State";
DataBlock DataBlk, desc="Data to be written (DMA write only)";
int Len, desc="...";
MachineID DmaRequestor, desc="DMA requestor";
}
external_type(TBETable) {
@ -243,8 +242,7 @@ machine(Directory, "Directory protocol")
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
dma_select_low_bit, dma_select_num_bits));
out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
@ -259,8 +257,7 @@ machine(Directory, "Directory protocol")
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
dma_select_low_bit, dma_select_num_bits));
out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
@ -271,8 +268,7 @@ machine(Directory, "Directory protocol")
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
dma_select_low_bit, dma_select_num_bits));
out_msg.Destination.add(TBEs[address].DmaRequestor);
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@ -343,6 +339,14 @@ machine(Directory, "Directory protocol")
TBEs[address].DataBlk := in_msg.DataBlk;
TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
TBEs[address].Len := in_msg.Len;
TBEs[address].DmaRequestor := in_msg.Requestor;
}
}
action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
peek(dmaRequestQueue_in, DMARequestMsg) {
TBEs.allocate(address);
TBEs[address].DmaRequestor := in_msg.Requestor;
}
}
@ -485,6 +489,7 @@ machine(Directory, "Directory protocol")
transition(I, DMA_READ, ID) {
//dr_sendDMAData;
r_allocateTbeForDmaRead;
qf_queueMemoryFetchRequestDMA;
p_popIncomingDMARequestQueue;
}
@ -492,6 +497,7 @@ machine(Directory, "Directory protocol")
transition(ID, Memory_Data, I) {
dr_sendDMAData;
//p_popIncomingDMARequestQueue;
w_deallocateTBE;
l_popMemQueue;
}

2
src/mem/protocol/MI_example-dma.sm
View file

@ -71,6 +71,7 @@ machine(DMA, "DMA Controller")
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
out_msg.Destination.add(map_Address_to_Directory(address));
@ -85,6 +86,7 @@ machine(DMA, "DMA Controller")
out_msg.PhysicalAddress := in_msg.PhysicalAddress;
out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
out_msg.Requestor := machineID;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
out_msg.Destination.add(map_Address_to_Directory(address));

1
src/mem/protocol/MI_example-msg.sm
View file

@ -105,6 +105,7 @@ structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
DMARequestType Type, desc="Request type (read/write)";
Address PhysicalAddress, desc="Physical address for this request";
Address LineAddress, desc="Line address for this request";
MachineID Requestor, desc="Node who initiated the request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
int Len, desc="The length of the request";

2
src/mem/ruby/config/MI_example.rb
View file

@ -23,8 +23,6 @@ class MI_example_DirectoryController < DirectoryController
def argv()
vec = super()
vec += " directory_latency "+directory_latency.to_s
vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
end
end