ruby: fixed dma mi example to work with multiple dma ports
This commit is contained in:
parent
f54790977b
commit
faf1d97f24
4 changed files with 18 additions and 11 deletions
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@ -1,8 +1,6 @@
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machine(Directory, "Directory protocol")
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machine(Directory, "Directory protocol")
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: int directory_latency,
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: int directory_latency
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int dma_select_low_bit,
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int dma_select_num_bits
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{
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{
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MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
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MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
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@ -74,6 +72,7 @@ machine(Directory, "Directory protocol")
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State TBEState, desc="Transient State";
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State TBEState, desc="Transient State";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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int Len, desc="...";
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int Len, desc="...";
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MachineID DmaRequestor, desc="DMA requestor";
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}
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}
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external_type(TBETable) {
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external_type(TBETable) {
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@ -243,8 +242,7 @@ machine(Directory, "Directory protocol")
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out_msg.LineAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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out_msg.Destination.add(TBEs[address].DmaRequestor);
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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}
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@ -259,8 +257,7 @@ machine(Directory, "Directory protocol")
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out_msg.LineAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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out_msg.Destination.add(TBEs[address].DmaRequestor);
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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}
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@ -271,8 +268,7 @@ machine(Directory, "Directory protocol")
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out_msg.PhysicalAddress := address;
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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out_msg.Destination.add(TBEs[address].DmaRequestor);
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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}
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@ -343,6 +339,14 @@ machine(Directory, "Directory protocol")
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TBEs[address].DataBlk := in_msg.DataBlk;
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TBEs[address].DataBlk := in_msg.DataBlk;
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TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
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TBEs[address].PhysicalAddress := in_msg.PhysicalAddress;
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TBEs[address].Len := in_msg.Len;
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TBEs[address].Len := in_msg.Len;
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TBEs[address].DmaRequestor := in_msg.Requestor;
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}
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}
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action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBEs.allocate(address);
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TBEs[address].DmaRequestor := in_msg.Requestor;
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}
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}
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}
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}
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@ -485,6 +489,7 @@ machine(Directory, "Directory protocol")
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transition(I, DMA_READ, ID) {
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transition(I, DMA_READ, ID) {
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//dr_sendDMAData;
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//dr_sendDMAData;
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r_allocateTbeForDmaRead;
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qf_queueMemoryFetchRequestDMA;
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qf_queueMemoryFetchRequestDMA;
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p_popIncomingDMARequestQueue;
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p_popIncomingDMARequestQueue;
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}
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}
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@ -492,6 +497,7 @@ machine(Directory, "Directory protocol")
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transition(ID, Memory_Data, I) {
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transition(ID, Memory_Data, I) {
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dr_sendDMAData;
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dr_sendDMAData;
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//p_popIncomingDMARequestQueue;
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//p_popIncomingDMARequestQueue;
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w_deallocateTBE;
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l_popMemQueue;
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l_popMemQueue;
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}
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}
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@ -71,6 +71,7 @@ machine(DMA, "DMA Controller")
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.Type := DMARequestType:READ;
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out_msg.Type := DMARequestType:READ;
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out_msg.Requestor := machineID;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Destination.add(map_Address_to_Directory(address));
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@ -85,6 +86,7 @@ machine(DMA, "DMA Controller")
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.PhysicalAddress := in_msg.PhysicalAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.LineAddress := in_msg.LineAddress;
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out_msg.Type := DMARequestType:WRITE;
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out_msg.Type := DMARequestType:WRITE;
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out_msg.Requestor := machineID;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.Len := in_msg.Len;
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out_msg.Len := in_msg.Len;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.Destination.add(map_Address_to_Directory(address));
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@ -105,6 +105,7 @@ structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
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DMARequestType Type, desc="Request type (read/write)";
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DMARequestType Type, desc="Request type (read/write)";
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Address PhysicalAddress, desc="Physical address for this request";
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Address PhysicalAddress, desc="Physical address for this request";
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Address LineAddress, desc="Line address for this request";
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Address LineAddress, desc="Line address for this request";
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MachineID Requestor, desc="Node who initiated the request";
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NetDest Destination, desc="Destination";
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NetDest Destination, desc="Destination";
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DataBlock DataBlk, desc="DataBlk attached to this request";
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DataBlock DataBlk, desc="DataBlk attached to this request";
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int Len, desc="The length of the request";
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int Len, desc="The length of the request";
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@ -23,8 +23,6 @@ class MI_example_DirectoryController < DirectoryController
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def argv()
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def argv()
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vec = super()
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vec = super()
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vec += " directory_latency "+directory_latency.to_s
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vec += " directory_latency "+directory_latency.to_s
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vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
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vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
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end
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end
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end
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end
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