sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Merge m5.eecs.umich.edu:/bk/newmem

Browse source 
into  ewok.(none):/home/gblack/m5/newmem

cpu/cpu_exec_context.cc:
    Hand merge

--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
This commit is contained in:
Gabe Black 2006-03-14 16:08:32 -05:00
commit fa763d2ecf
30 changed files with 1255 additions and 891 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/SConscript
View file

@ -50,7 +50,7 @@ isa_switch_hdrs = Split('''
faults.hh faults.hh
isa_traits.hh isa_traits.hh
process.hh process.hh
registerfile.hh regfile.hh
stacktrace.hh stacktrace.hh
tlb.hh tlb.hh
types.hh types.hh

2
arch/alpha/arguments.cc
View file

@ -54,7 +54,7 @@ AlphaArguments::getArg(bool fp)
{ {
if (number < 6) { if (number < 6) {
if (fp) if (fp)
return xc->readFloatRegInt(16 + number); return xc->readFloatRegBits(16 + number);
else else
return xc->readIntReg(16 + number); return xc->readIntReg(16 + number);
} else { } else {

2
arch/alpha/ev5.cc
View file

@ -134,7 +134,7 @@ AlphaISA::zeroRegisters(CPU *cpu)
// (no longer very clean due to the change in setIntReg() in the // (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.) // cpu model. Consider changing later.)
cpu->cpuXC->setIntReg(ZeroReg, 0); cpu->cpuXC->setIntReg(ZeroReg, 0);
cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0); cpu->cpuXC->setFloatReg(ZeroReg, 0.0);
} }
Fault Fault

2
arch/alpha/isa_traits.hh
View file

@ -33,7 +33,7 @@ namespace LittleEndianGuest {}
#include "arch/alpha/types.hh" #include "arch/alpha/types.hh"
#include "arch/alpha/constants.hh" #include "arch/alpha/constants.hh"
#include "arch/alpha/registerfile.hh" #include "arch/alpha/regfile.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "sim/host.hh" #include "sim/host.hh"

66
arch/alpha/registerfile.hh → arch/alpha/regfile.hh
View file

@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef __ARCH_ALPHA_REGISTERFILE_HH__ #ifndef __ARCH_ALPHA_REGFILE_HH__
#define __ARCH_ALPHA_REGISTERFILE_HH__ #define __ARCH_ALPHA_REGFILE_HH__
#include "arch/alpha/types.hh" #include "arch/alpha/types.hh"
#include "arch/alpha/constants.hh" #include "arch/alpha/constants.hh"
@ -41,10 +41,64 @@ namespace AlphaISA
typedef IntReg IntRegFile[NumIntRegs]; typedef IntReg IntRegFile[NumIntRegs];
typedef union { class FloatRegFile
uint64_t q[NumFloatRegs]; // integer qword view {
double d[NumFloatRegs]; // double-precision floating point view protected:
} FloatRegFile;
union {
uint64_t q[NumFloatRegs]; // integer qword view
double d[NumFloatRegs]; // double-precision floating point view
};
public:
FloatReg readReg(int floatReg)
{
return d[floatReg];
}
FloatReg readReg(int floatReg, int width)
{
return readReg(floatReg);
}
FloatRegBits readRegBits(int floatReg)
{
return q[floatReg];
}
FloatRegBits readRegBits(int floatReg, int width)
{
return readRegBits(floatReg);
}
Fault setReg(int floatReg, const FloatReg &val)
{
d[floatReg] = val;
return NoFault;
}
Fault setReg(int floatReg, const FloatReg &val, int width)
{
return setReg(floatReg, val);
}
Fault setRegBits(int floatReg, const FloatRegBits &val)
{
q[floatReg] = val;
return NoFault;
}
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
return setRegBits(floatReg, val);
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
class MiscRegFile { class MiscRegFile {
protected: protected:

6
arch/alpha/types.hh
View file

@ -54,10 +54,8 @@ namespace AlphaISA
typedef uint64_t IntReg; typedef uint64_t IntReg;
// floating point register file entry type // floating point register file entry type
typedef union { typedef double FloatReg;
uint64_t q; typedef uint64_t FloatRegBits;
double d;
} FloatReg;
// control register file contents // control register file contents
typedef uint64_t MiscReg; typedef uint64_t MiscReg;

2
arch/alpha/utility.hh
View file

@ -32,7 +32,7 @@
#include "config/full_system.hh" #include "config/full_system.hh"
#include "arch/alpha/types.hh" #include "arch/alpha/types.hh"
#include "arch/alpha/constants.hh" #include "arch/alpha/constants.hh"
#include "arch/alpha/registerfile.hh" #include "arch/alpha/regfile.hh"
#include "base/misc.hh" #include "base/misc.hh"
namespace AlphaISA namespace AlphaISA

34
arch/isa_parser.py
View file

@ -1217,16 +1217,23 @@ class FloatRegOperand(Operand):
def makeRead(self): def makeRead(self):
bit_select = 0 bit_select = 0
width = 0;
if (self.ctype == 'float'): if (self.ctype == 'float'):
func = 'readFloatRegSingle' func = 'readFloatReg'
width = 32;
elif (self.ctype == 'double'): elif (self.ctype == 'double'):
func = 'readFloatRegDouble' func = 'readFloatReg'
width = 64;
else: else:
func = 'readFloatRegInt' func = 'readFloatRegBits'
if (self.size != self.dflt_size): if (self.size != self.dflt_size):
bit_select = 1 bit_select = 1
base = 'xc->%s(this, %d)' % \ if width:
(func, self.src_reg_idx) base = 'xc->%s(this, %d, %d)' % \
(func, self.src_reg_idx, width)
else:
base = 'xc->%s(this, %d)' % \
(func, self.src_reg_idx)
if bit_select: if bit_select:
return '%s = bits(%s, %d, 0);\n' % \ return '%s = bits(%s, %d, 0);\n' % \
(self.base_name, base, self.size-1) (self.base_name, base, self.size-1)
@ -1236,21 +1243,28 @@ class FloatRegOperand(Operand):
def makeWrite(self): def makeWrite(self):
final_val = self.base_name final_val = self.base_name
final_ctype = self.ctype final_ctype = self.ctype
widthSpecifier = ''
width = 0
if (self.ctype == 'float'): if (self.ctype == 'float'):
func = 'setFloatRegSingle' width = 32
func = 'setFloatReg'
elif (self.ctype == 'double'): elif (self.ctype == 'double'):
func = 'setFloatRegDouble' width = 64
func = 'setFloatReg'
else: else:
func = 'setFloatRegInt' func = 'setFloatRegBits'
final_ctype = 'uint%d_t' % self.dflt_size final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed): if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name) final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
if width:
widthSpecifier = ', %d' % width
wb = ''' wb = '''
{ {
%s final_val = %s; %s final_val = %s;
xc->%s(this, %d, final_val);\n xc->%s(this, %d, final_val%s);\n
if (traceData) { traceData->setData(final_val); } if (traceData) { traceData->setData(final_val); }
}''' % (final_ctype, final_val, func, self.dest_reg_idx) }''' % (final_ctype, final_val, func, self.dest_reg_idx,
widthSpecifier)
return wb return wb
class ControlRegOperand(Operand): class ControlRegOperand(Operand):

3
arch/sparc/SConscript
View file

@ -57,8 +57,7 @@ full_system_sources = Split('''
# Syscall emulation (non-full-system) sources # Syscall emulation (non-full-system) sources
syscall_emulation_sources = Split(''' syscall_emulation_sources = Split('''
common_syscall_emul.cc linux/process.cc
linux_process.cc
process.cc process.cc
''') ''')

4
arch/sparc/isa/base.isa
View file

@ -11,7 +11,7 @@ output header {{
uint8_t v:1; uint8_t v:1;
uint8_t z:1; uint8_t z:1;
uint8_t n:1; uint8_t n:1;
} };
enum condTest enum condTest
{ {
@ -31,7 +31,7 @@ output header {{
Negative=0x6, Negative=0x6,
OverflowClear=0xF, OverflowClear=0xF,
OverflowSet=0x7 OverflowSet=0x7
} };
/** /**
* Base class for all SPARC static instructions. * Base class for all SPARC static instructions.

2
arch/sparc/isa/decoder.isa
View file

@ -6,7 +6,7 @@
decode OP default Trap::unknown({{IllegalInstruction}}) { decode OP default Trap::unknown({{IllegalInstruction}}) {
0x0: decode OP2 { 0x0: decode OP2 {
0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP //0x0: Trap::illtrap({{IllegalInstruction}}); //ILLTRAP
0x1: Branch::bpcc({{ 0x1: Branch::bpcc({{
switch((CC12 << 1) | CC02) switch((CC12 << 1) | CC02)
{ {

4
arch/sparc/isa/includes.isa
View file

@ -10,7 +10,7 @@ output header {{
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "arch/sparc/faults.hh" #include "arch/sparc/faults.hh"
#include "mem/mem_req.hh" // some constructors use MemReq flags #include "mem/request.hh" // some constructors use MemReq flags
#include "arch/sparc/isa_traits.hh" #include "arch/sparc/isa_traits.hh"
}}; }};
@ -34,7 +34,7 @@ output exec {{
#endif #endif
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
//#include "arch/alpha/pseudo_inst.hh" //#include "sim/pseudo_inst.hh"
#endif #endif
#include "cpu/base.hh" #include "cpu/base.hh"
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"

554
arch/sparc/isa_traits.hh
View file

@ -29,457 +29,19 @@
#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
#define __ARCH_SPARC_ISA_TRAITS_HH__ #define __ARCH_SPARC_ISA_TRAITS_HH__
#include "arch/sparc/faults.hh"
#include "base/misc.hh" #include "base/misc.hh"
#include "config/full_system.hh" #include "config/full_system.hh"
#include "sim/host.hh" #include "sim/host.hh"
//This makes sure the big endian versions of certain functions are used.
namespace BigEndianGuest {}
using namespace BigEndianGuest;
class ExecContext; class ExecContext;
class FastCPU; class FastCPU;
//class FullCPU; //class FullCPU;
class Checkpoint; class Checkpoint;
#define TARGET_SPARC
class StaticInst; class StaticInst;
class StaticInstPtr; class StaticInstPtr;
//namespace EV5 namespace BigEndianGuest {}
//{
// int DTB_ASN_ASN(uint64_t reg);
// int ITB_ASN_ASN(uint64_t reg);
//}
namespace SparcISA
{
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
const int NumFloatRegs = 32;
const int NumMiscRegs = 32;
const int // Maximum trap level
const int MaxTL = 4;
const int
const int // semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
const int // the rest of these depend on the ABI
const int StackPointerReg = 14;
const int ReturnAddressReg = 31; // post call, precall is 15
const int ReturnValueReg = 8; // Post return, 24 is pre-return.
const int FramePointerReg = 30;
const int ArgumentReg0 = 8;
const int ArgumentReg1 = 9;
const int ArgumentReg2 = 10;
const int ArgumentReg3 = 11;
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
// Some OS syscall sue a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;
//8K. This value is implmentation specific; and should probably
//be somewhere else.
const int LogVMPageSize = 13;
const int VMPageSize = (1 << LogVMPageSize);
typedef uint64_t IntReg;
class IntRegFile
{
private:
//For right now, let's pretend the register file is static
IntReg regs[32];
public:
IntReg & operator [] (RegIndex index)
{
//Don't allow indexes outside of the 32 registers
index &= 0x1F;
return regs[index];
}
};
void serialize(std::ostream & os);
void unserialize(Checkpoint *cp, const std::string &section);
typedef float float32_t;
typedef double float64_t;
//FIXME This actually usually refers to a 10 byte float, rather than a
//16 byte float as required. This data type may have to be emulated.
typedef long double float128_t;
class FloatRegFile
{
private:
//By using the largest data type, we ensure everything
//is aligned correctly in memory
union
{
float128_t rawRegs[16];
uint64_t regDump[32];
};
class QuadRegs
{
private:
FloatRegFile * parent;
public:
QuadRegs(FloatRegFile * p) : parent(p) {;}
float128_t & operator [] (RegIndex index)
{
//Quad floats are index by the single
//precision register the start on,
//and only 16 should be accessed
index = (index >> 2) & 0xF;
return parent->rawRegs[index];
}
};
class DoubleRegs
{
private:
FloatRegFile * parent;
public:
DoubleRegs(FloatRegFile * p) : parent(p) {;}
float64_t & operator [] (RegIndex index)
{
//Double floats are index by the single
//precision register the start on,
//and only 32 should be accessed
index = (index >> 1) & 0x1F;
return ((float64_t *)parent->rawRegs)[index];
}
};
class SingleRegs
{
private:
FloatRegFile * parent;
public:
SingleRegs(FloatRegFile * p) : parent(p) {;}
float32_t & operator [] (RegIndex index)
{
//Only 32 single floats should be accessed
index &= 0x1F;
return ((float32_t *)parent->rawRegs)[index];
}
};
public:
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, std::string & section);
QuadRegs quadRegs;
DoubleRegs doubleRegs;
SingleRegs singleRegs;
FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
{;}
};
// control register file contents
typedef uint64_t MiscReg;
// The control registers, broken out into fields
class MiscRegFile
{
private:
union
{
uint16_t pstate; // Process State Register
struct
{
uint16_t ag:1; // Alternate Globals
uint16_t ie:1; // Interrupt enable
uint16_t priv:1; // Privelege mode
uint16_t am:1; // Address mask
uint16_t pef:1; // PSTATE enable floating-point
uint16_t red:1; // RED (reset, error, debug) state
uint16_t mm:2; // Memory Model
uint16_t tle:1; // Trap little-endian
uint16_t cle:1; // Current little-endian
} pstateFields;
};
uint64_t tba; // Trap Base Address
union
{
uint64_t y; // Y (used in obsolete multiplication)
struct
{
uint64_t value:32; // The actual value stored in y
uint64_t :32; // reserved bits
} yFields;
};
uint8_t pil; // Process Interrupt Register
uint8_t cwp; // Current Window Pointer
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
// on the previous level)
union
{
uint8_t ccr; // Condition Code Register
struct
{
union
{
uint8_t icc:4; // 32-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} iccFields;
};
union
{
uint8_t xcc:4; // 64-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} xccFields;
};
} ccrFields;
};
uint8_t asi; // Address Space Identifier
uint8_t tl; // Trap Level
uint64_t tpc[MaxTL]; // Trap Program Counter (value from
// previous trap level)
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
// previous trap level)
union
{
uint64_t tstate[MaxTL]; // Trap State
struct
{
//Values are from previous trap level
uint64_t cwp:5; // Current Window Pointer
uint64_t :2; // Reserved bits
uint64_t pstate:10; // Process State
uint64_t :6; // Reserved bits
uint64_t asi:8; // Address Space Identifier
uint64_t ccr:8; // Condition Code Register
} tstateFields[MaxTL];
};
union
{
uint64_t tick; // Hardware clock-tick counter
struct
{
uint64_t counter:63; // Clock-tick count
uint64_t npt:1; // Non-priveleged trap
} tickFields;
};
uint8_t cansave; // Savable windows
uint8_t canrestore; // Restorable windows
uint8_t otherwin; // Other windows
uint8_t cleanwin; // Clean windows
union
{
uint8_t wstate; // Window State
struct
{
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
// register window trap
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
// register window trap
} wstateFields;
};
union
{
uint64_t ver; // Version
struct
{
uint64_t maxwin:5; // Max CWP value
uint64_t :2; // Reserved bits
uint64_t maxtl:8; // Maximum trap level
uint64_t :8; // Reserved bits
uint64_t mask:8; // Processor mask set revision number
uint64_t impl:16; // Implementation identification number
uint64_t manuf:16; // Manufacturer code
} verFields;
};
union
{
uint64_t fsr; // Floating-Point State Register
struct
{
union
{
uint64_t cexc:5; // Current excpetion
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} cexecFields;
};
union
{
uint64_t aexc:5; // Accrued exception
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} aexecFields;
};
uint64_t fcc0:2; // Floating-Point condtion codes
uint64_t :1; // Reserved bits
uint64_t qne:1; // Deferred trap queue not empty
// with no queue, it should read 0
uint64_t ftt:3; // Floating-Point trap type
uint64_t ver:3; // Version (of the FPU)
uint64_t :2; // Reserved bits
uint64_t ns:1; // Nonstandard floating point
union
{
uint64_t tem:5; // Trap Enable Mask
struct
{
uint64_t nxm:1; // Inexact
uint64_t dzm:1; // Divide by zero
uint64_t ufm:1; // Underflow
uint64_t ofm:1; // Overflow
uint64_t nvm:1; // Invalid operand
} temFields;
};
uint64_t :2; // Reserved bits
uint64_t rd:2; // Rounding direction
uint64_t fcc1:2; // Floating-Point condition codes
uint64_t fcc2:2; // Floating-Point condition codes
uint64_t fcc3:2; // Floating-Point condition codes
uint64_t :26; // Reserved bits
} fsrFields;
};
union
{
uint8_t fprs; // Floating-Point Register State
struct
{
uint8_t dl:1; // Dirty lower
uint8_t du:1; // Dirty upper
uint8_t fef:1; // FPRS enable floating-Point
} fprsFields;
};
public:
MiscReg readReg(int misc_reg);
MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
Fault setReg(int misc_reg, const MiscReg &val);
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
ExecContext *xc);
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, std::string & section);
};
typedef union
{
float32_t singReg;
float64_t doubReg;
float128_t quadReg;
} FloatReg;
typedef union
{
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
struct RegFile
{
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegFile; // control register file
Addr pc; // Program Counter
Addr npc; // Next Program Counter
Addr nnpc;
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
// Instruction address compression hooks
inline Addr realPCToFetchPC(const Addr &addr)
{
return addr;
}
inline Addr fetchPCToRealPC(const Addr &addr)
{
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
inline size_t fetchInstSize()
{
return sizeof(MachInst);
}
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
static inline setSyscallReturn(SyscallReturn return_value, RegFile *regs)
{
// check for error condition. SPARC syscall convention is to
// indicate success/failure in reg the carry bit of the ccr
// and put the return value itself in the standard return value reg ().
if (return_value.successful()) {
// no error
regs->miscRegFile.ccrFields.iccFields.c = 0;
regs->intRegFile[ReturnValueReg] = return_value.value();
} else {
// got an error, return details
regs->miscRegFile.ccrFields.iccFields.c = 1;
regs->intRegFile[ReturnValueReg] = -return_value.value();
}
}
};
#if !FULL_SYSTEM #if !FULL_SYSTEM
class SyscallReturn class SyscallReturn
@ -519,9 +81,119 @@ class SyscallReturn
#endif #endif
#if FULL_SYSTEM namespace SparcISA
{
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
#include "arch/alpha/ev5.hh" typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
const int NumIntRegs = 32;
const int NumFloatRegs = 64;
const int NumMiscRegs = 32;
// semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful
// the rest of these depend on the ABI
const int StackPointerReg = 14;
const int ReturnAddressReg = 31; // post call, precall is 15
const int ReturnValueReg = 8; // Post return, 24 is pre-return.
const int FramePointerReg = 30;
const int ArgumentReg0 = 8;
const int ArgumentReg1 = 9;
const int ArgumentReg2 = 10;
const int ArgumentReg3 = 11;
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
// Some OS syscall sue a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;
//XXX These numbers are bogus
const int MaxInstSrcRegs = 3;
const int MaxInstDestRegs = 2;
typedef uint64_t IntReg;
// control register file contents
typedef uint64_t MiscReg;
typedef double FloatReg;
typedef uint64_t FloatRegBits;
//8K. This value is implmentation specific; and should probably
//be somewhere else.
const int LogVMPageSize = 13;
const int VMPageSize = (1 << LogVMPageSize);
//Why does both the previous set of constants and this one exist?
const int PageShift = 13;
const int PageBytes = ULL(1) << PageShift;
const int BranchPredAddrShiftAmt = 2;
const int WordBytes = 4;
const int HalfwordBytes = 2;
const int ByteBytes = 1;
void serialize(std::ostream & os);
void unserialize(Checkpoint *cp, const std::string &section);
StaticInstPtr decodeInst(MachInst);
// return a no-op instruction... used for instruction fetch faults
extern const MachInst NoopMachInst;
// Instruction address compression hooks
inline Addr realPCToFetchPC(const Addr &addr)
{
return addr;
}
inline Addr fetchPCToRealPC(const Addr &addr)
{
return addr;
}
// the size of "fetched" instructions (not necessarily the size
// of real instructions for PISA)
inline size_t fetchInstSize()
{
return sizeof(MachInst);
}
/**
* Function to insure ISA semantics about 0 registers.
* @param xc The execution context.
*/
template <class XC>
void zeroRegisters(XC *xc);
}
#include "arch/sparc/regfile.hh"
namespace SparcISA
{
#if !FULL_SYSTEM
static inline void setSyscallReturn(SyscallReturn return_value,
RegFile *regs)
{
// check for error condition. SPARC syscall convention is to
// indicate success/failure in reg the carry bit of the ccr
// and put the return value itself in the standard return value reg ().
if (return_value.successful()) {
// no error
regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 0);
regs->intRegFile[ReturnValueReg] = return_value.value();
} else {
// got an error, return details
regs->miscRegs.setReg(MISCREG_CCR_ICC_C, 1);
regs->intRegFile[ReturnValueReg] = -return_value.value();
}
}
#endif #endif
};
#endif // __ARCH_SPARC_ISA_TRAITS_HH__ #endif // __ARCH_SPARC_ISA_TRAITS_HH__

580
arch/sparc/linux/process.cc
View file

@ -26,14 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/ */
#include "arch/sparc/common_syscall_emul.hh"
#include "arch/sparc/linux/process.hh" #include "arch/sparc/linux/process.hh"
#include "arch/sparc/isa_traits.hh" #include "arch/sparc/isa_traits.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "cpu/exec_context.hh" #include "cpu/exec_context.hh"
#include "kern/linux/linux.hh" #include "kern/linux/linux.hh"
#include "mem/functional/functional.hh"
#include "sim/process.hh" #include "sim/process.hh"
#include "sim/syscall_emul.hh" #include "sim/syscall_emul.hh"
@ -55,318 +53,318 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "sparc"); strcpy(name->machine, "sparc");
name.copyOut(xc->mem); name.copyOut(xc->getMemPort());
return 0; return 0;
} }
SyscallDesc SparcLinuxProcess::syscallDescs[] = { SyscallDesc SparcLinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("restart_syscall", unimplementedFunc); /* 0 */ SyscallDesc("restart_syscall", unimplementedFunc),
/* 1 */ SyscallDesc("exit", exitFunc); /* 1 */ SyscallDesc("exit", exitFunc),
/* 2 */ SyscallDesc("fork", unimplementedFunc); /* 2 */ SyscallDesc("fork", unimplementedFunc),
/* 3 */ SyscallDesc("read", readFunc); /* 3 */ SyscallDesc("read", readFunc),
/* 4 */ SyscallDesc("write", writeFunc); /* 4 */ SyscallDesc("write", writeFunc),
/* 5 */ SyscallDesc("open", openFunc<Linux>); /* 5 */ SyscallDesc("open", openFunc<Linux>),
/* 6 */ SyscallDesc("close", closeFinc); /* 6 */ SyscallDesc("close", closeFunc),
/* 7 */ SyscallDesc("wait4", unimplementedFunc); /* 7 */ SyscallDesc("wait4", unimplementedFunc),
/* 8 */ SyscallDesc("creat", unimplementedFunc); /* 8 */ SyscallDesc("creat", unimplementedFunc),
/* 9 */ SyscallDesc("link", unimplementedFunc); /* 9 */ SyscallDesc("link", unimplementedFunc),
/* 10 */ SyscallDesc("unlink", unlinkFunc); /* 10 */ SyscallDesc("unlink", unlinkFunc),
/* 11 */ SyscallDesc("execv", unimplementedFunc); /* 11 */ SyscallDesc("execv", unimplementedFunc),
/* 12 */ SyscallDesc("chdir", unimplementedFunc); /* 12 */ SyscallDesc("chdir", unimplementedFunc),
/* 13 */ SyscallDesc("chown", chownFunc); /* 13 */ SyscallDesc("chown", chownFunc),
/* 14 */ SyscallDesc("mknod", unimplementedFunc); /* 14 */ SyscallDesc("mknod", unimplementedFunc),
/* 15 */ SyscallDesc("chmod", chmodFunc<Linux>); /* 15 */ SyscallDesc("chmod", chmodFunc<Linux>),
/* 16 */ SyscallDesc("lchown", unimplementedFunc); /* 16 */ SyscallDesc("lchown", unimplementedFunc),
/* 17 */ SyscallDesc("brk", obreakFunc); /* 17 */ SyscallDesc("brk", obreakFunc),
/* 18 */ SyscallDesc("perfctr", unimplementedFunc); /* 18 */ SyscallDesc("perfctr", unimplementedFunc),
/* 19 */ SyscallDesc("lseek", lseekFunc); /* 19 */ SyscallDesc("lseek", lseekFunc),
/* 20 */ SyscallDesc("getpid", getpidFunc); /* 20 */ SyscallDesc("getpid", getpidFunc),
/* 21 */ SyscallDesc("capget", unimplementedFunc); /* 21 */ SyscallDesc("capget", unimplementedFunc),
/* 22 */ SyscallDesc("capset", unimplementedFunc); /* 22 */ SyscallDesc("capset", unimplementedFunc),
/* 23 */ SyscallDesc("setuid", setuidFunc); /* 23 */ SyscallDesc("setuid", setuidFunc),
/* 24 */ SyscallDesc("getuid", getuidFunc); /* 24 */ SyscallDesc("getuid", getuidFunc),
/* 25 */ SyscallDesc("time", unimplementedFunc); /* 25 */ SyscallDesc("time", unimplementedFunc),
/* 26 */ SyscallDesc("ptrace", unimplementedFunc); /* 26 */ SyscallDesc("ptrace", unimplementedFunc),
/* 27 */ SyscallDesc("alarm", unimplementedFunc); /* 27 */ SyscallDesc("alarm", unimplementedFunc),
/* 28 */ SyscallDesc("sigaltstack", unimplementedFunc); /* 28 */ SyscallDesc("sigaltstack", unimplementedFunc),
/* 29 */ SyscallDesc("pause", unimplementedFunc); /* 29 */ SyscallDesc("pause", unimplementedFunc),
/* 30 */ SyscallDesc("utime", unimplementedFunc); /* 30 */ SyscallDesc("utime", unimplementedFunc),
/* 31 */ SyscallDesc("lchown32", unimplementedFunc); /* 31 */ SyscallDesc("lchown32", unimplementedFunc),
/* 32 */ SyscallDesc("fchown32", unimplementedFunc); /* 32 */ SyscallDesc("fchown32", unimplementedFunc),
/* 33 */ SyscallDesc("access", unimplementedFunc); /* 33 */ SyscallDesc("access", unimplementedFunc),
/* 34 */ SyscallDesc("nice", unimplementedFunc); /* 34 */ SyscallDesc("nice", unimplementedFunc),
/* 35 */ SyscallDesc("chown32", unimplementedFunc); /* 35 */ SyscallDesc("chown32", unimplementedFunc),
/* 36 */ SyscallDesc("sync", unimplementedFunc); /* 36 */ SyscallDesc("sync", unimplementedFunc),
/* 37 */ SyscallDesc("kill", unimplementedFunc); /* 37 */ SyscallDesc("kill", unimplementedFunc),
/* 38 */ SyscallDesc("stat", unimplementedFunc); /* 38 */ SyscallDesc("stat", unimplementedFunc),
/* 39 */ SyscallDesc("sendfile", unimplementedFunc); /* 39 */ SyscallDesc("sendfile", unimplementedFunc),
/* 40 */ SyscallDesc("lstat", unimplementedFunc); /* 40 */ SyscallDesc("lstat", unimplementedFunc),
/* 41 */ SyscallDesc("dup", unimplementedFunc); /* 41 */ SyscallDesc("dup", unimplementedFunc),
/* 42 */ SyscallDesc("pipe", pipePseudoFunc); /* 42 */ SyscallDesc("pipe", pipePseudoFunc),
/* 43 */ SyscallDesc("times", unimplementedFunc); /* 43 */ SyscallDesc("times", unimplementedFunc),
/* 44 */ SyscallDesc("getuid32", unimplementedFunc); /* 44 */ SyscallDesc("getuid32", unimplementedFunc),
/* 45 */ SyscallDesc("umount2", unimplementedFunc); /* 45 */ SyscallDesc("umount2", unimplementedFunc),
/* 46 */ SyscallDesc("setgid", unimplementedFunc); /* 46 */ SyscallDesc("setgid", unimplementedFunc),
/* 47 */ SyscallDesc("getgid", getgidFunc); /* 47 */ SyscallDesc("getgid", getgidFunc),
/* 48 */ SyscallDesc("signal", unimplementedFunc); /* 48 */ SyscallDesc("signal", unimplementedFunc),
/* 49 */ SyscallDesc("geteuid", geteuidFunc); /* 49 */ SyscallDesc("geteuid", geteuidFunc),
/* 50 */ SyscallDesc("getegid", getegidFunc); /* 50 */ SyscallDesc("getegid", getegidFunc),
/* 51 */ SyscallDesc("acct", unimplementedFunc); /* 51 */ SyscallDesc("acct", unimplementedFunc),
/* 52 */ SyscallDesc("memory_ordering", unimplementedFunc); /* 52 */ SyscallDesc("memory_ordering", unimplementedFunc),
/* 53 */ SyscallDesc("getgid32", unimplementedFunc); /* 53 */ SyscallDesc("getgid32", unimplementedFunc),
/* 54 */ SyscallDesc("ioctl", unimplementedFunc); /* 54 */ SyscallDesc("ioctl", unimplementedFunc),
/* 55 */ SyscallDesc("reboot", unimplementedFunc); /* 55 */ SyscallDesc("reboot", unimplementedFunc),
/* 56 */ SyscallDesc("mmap2", unimplementedFunc); /* 56 */ SyscallDesc("mmap2", unimplementedFunc),
/* 57 */ SyscallDesc("symlink", unimplementedFunc); /* 57 */ SyscallDesc("symlink", unimplementedFunc),
/* 58 */ SyscallDesc("readlink", unimplementedFunc); /* 58 */ SyscallDesc("readlink", unimplementedFunc),
/* 59 */ SyscallDesc("execve", unimplementedFunc); /* 59 */ SyscallDesc("execve", unimplementedFunc),
/* 60 */ SyscallDesc("umask", unimplementedFunc); /* 60 */ SyscallDesc("umask", unimplementedFunc),
/* 61 */ SyscallDesc("chroot", unimplementedFunc); /* 61 */ SyscallDesc("chroot", unimplementedFunc),
/* 62 */ SyscallDesc("fstat", unimplementedFunc); /* 62 */ SyscallDesc("fstat", unimplementedFunc),
/* 63 */ SyscallDesc("fstat64", unimplementedFunc); /* 63 */ SyscallDesc("fstat64", unimplementedFunc),
/* 64 */ SyscallDesc("getpagesize", unimplementedFunc); /* 64 */ SyscallDesc("getpagesize", unimplementedFunc),
/* 65 */ SyscallDesc("msync", unimplementedFunc); /* 65 */ SyscallDesc("msync", unimplementedFunc),
/* 66 */ SyscallDesc("vfork", unimplementedFunc); /* 66 */ SyscallDesc("vfork", unimplementedFunc),
/* 67 */ SyscallDesc("pread64", unimplementedFunc); /* 67 */ SyscallDesc("pread64", unimplementedFunc),
/* 68 */ SyscallDesc("pwrite64", unimplementedFunc); /* 68 */ SyscallDesc("pwrite64", unimplementedFunc),
/* 69 */ SyscallDesc("geteuid32", unimplementedFunc); /* 69 */ SyscallDesc("geteuid32", unimplementedFunc),
/* 70 */ SyscallDesc("getdgid32", unimplementedFunc); /* 70 */ SyscallDesc("getdgid32", unimplementedFunc),
/* 71 */ SyscallDesc("mmap", unimplementedFunc); /* 71 */ SyscallDesc("mmap", unimplementedFunc),
/* 72 */ SyscallDesc("setreuid32", unimplementedFunc); /* 72 */ SyscallDesc("setreuid32", unimplementedFunc),
/* 73 */ SyscallDesc("munmap", unimplementedFunc); /* 73 */ SyscallDesc("munmap", unimplementedFunc),
/* 74 */ SyscallDesc("mprotect", unimplementedFunc); /* 74 */ SyscallDesc("mprotect", unimplementedFunc),
/* 75 */ SyscallDesc("madvise", unimplementedFunc); /* 75 */ SyscallDesc("madvise", unimplementedFunc),
/* 76 */ SyscallDesc("vhangup", unimplementedFunc); /* 76 */ SyscallDesc("vhangup", unimplementedFunc),
/* 77 */ SyscallDesc("truncate64", unimplementedFunc); /* 77 */ SyscallDesc("truncate64", unimplementedFunc),
/* 78 */ SyscallDesc("mincore", unimplementedFunc); /* 78 */ SyscallDesc("mincore", unimplementedFunc),
/* 79 */ SyscallDesc("getgroups", unimplementedFunc); /* 79 */ SyscallDesc("getgroups", unimplementedFunc),
/* 80 */ SyscallDesc("setgroups", unimplementedFunc); /* 80 */ SyscallDesc("setgroups", unimplementedFunc),
/* 81 */ SyscallDesc("getpgrp", unimplementedFunc); /* 81 */ SyscallDesc("getpgrp", unimplementedFunc),
/* 82 */ SyscallDesc("setgroups32", unimplementedFunc); /* 82 */ SyscallDesc("setgroups32", unimplementedFunc),
/* 83 */ SyscallDesc("setitimer", unimplementedFunc); /* 83 */ SyscallDesc("setitimer", unimplementedFunc),
/* 84 */ SyscallDesc("ftruncate64", unimplementedFunc); /* 84 */ SyscallDesc("ftruncate64", unimplementedFunc),
/* 85 */ SyscallDesc("swapon", unimplementedFunc); /* 85 */ SyscallDesc("swapon", unimplementedFunc),
/* 86 */ SyscallDesc("getitimer", unimplementedFunc); /* 86 */ SyscallDesc("getitimer", unimplementedFunc),
/* 87 */ SyscallDesc("setuid32", unimplementedFunc); /* 87 */ SyscallDesc("setuid32", unimplementedFunc),
/* 88 */ SyscallDesc("sethostname", unimplementedFunc); /* 88 */ SyscallDesc("sethostname", unimplementedFunc),
/* 89 */ SyscallDesc("setgid32", unimplementedFunc); /* 89 */ SyscallDesc("setgid32", unimplementedFunc),
/* 90 */ SyscallDesc("dup2", unimplementedFunc); /* 90 */ SyscallDesc("dup2", unimplementedFunc),
/* 91 */ SyscallDesc("setfsuid32", unimplementedFunc); /* 91 */ SyscallDesc("setfsuid32", unimplementedFunc),
/* 92 */ SyscallDesc("fcntl", unimplementedFunc); /* 92 */ SyscallDesc("fcntl", unimplementedFunc),
/* 93 */ SyscallDesc("select", unimplementedFunc); /* 93 */ SyscallDesc("select", unimplementedFunc),
/* 94 */ SyscallDesc("setfsgid32", unimplementedFunc); /* 94 */ SyscallDesc("setfsgid32", unimplementedFunc),
/* 95 */ SyscallDesc("fsync", unimplementedFunc); /* 95 */ SyscallDesc("fsync", unimplementedFunc),
/* 96 */ SyscallDesc("setpriority", unimplementedFunc); /* 96 */ SyscallDesc("setpriority", unimplementedFunc),
/* 97 */ SyscallDesc("socket", unimplementedFunc); /* 97 */ SyscallDesc("socket", unimplementedFunc),
/* 98 */ SyscallDesc("connect", unimplementedFunc); /* 98 */ SyscallDesc("connect", unimplementedFunc),
/* 99 */ SyscallDesc("accept", unimplementedFunc); /* 99 */ SyscallDesc("accept", unimplementedFunc),
/* 100 */ SyscallDesc("getpriority", unimplementedFunc); /* 100 */ SyscallDesc("getpriority", unimplementedFunc),
/* 101 */ SyscallDesc("rt_sigreturn", unimplementedFunc); /* 101 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
/* 102 */ SyscallDesc("rt_sigaction", unimplementedFunc); /* 102 */ SyscallDesc("rt_sigaction", unimplementedFunc),
/* 103 */ SyscallDesc("rt_sigprocmask", unimplementedFunc); /* 103 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
/* 104 */ SyscallDesc("rt_sigpending", unimplementedFunc); /* 104 */ SyscallDesc("rt_sigpending", unimplementedFunc),
/* 105 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc); /* 105 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
/* 106 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc); /* 106 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc),
/* 107 */ SyscallDesc("rt_sigsuspend", unimplementedFunc); /* 107 */ SyscallDesc("rt_sigsuspend", unimplementedFunc),
/* 108 */ SyscallDesc("setresuid", unimplementedFunc); /* 108 */ SyscallDesc("setresuid", unimplementedFunc),
/* 109 */ SyscallDesc("getresuid", unimplementedFunc); /* 109 */ SyscallDesc("getresuid", unimplementedFunc),
/* 110 */ SyscallDesc("setresgid", unimplementedFunc); /* 110 */ SyscallDesc("setresgid", unimplementedFunc),
/* 111 */ SyscallDesc("getresgid", unimplementedFunc); /* 111 */ SyscallDesc("getresgid", unimplementedFunc),
/* 112 */ SyscallDesc("setregid32", unimplementedFunc); /* 112 */ SyscallDesc("setregid32", unimplementedFunc),
/* 113 */ SyscallDesc("recvmsg", unimplementedFunc); /* 113 */ SyscallDesc("recvmsg", unimplementedFunc),
/* 114 */ SyscallDesc("sendmsg", unimplementedFunc); /* 114 */ SyscallDesc("sendmsg", unimplementedFunc),
/* 115 */ SyscallDesc("getgroups32", unimplementedFunc); /* 115 */ SyscallDesc("getgroups32", unimplementedFunc),
/* 116 */ SyscallDesc("gettimeofday", unimplementedFunc); /* 116 */ SyscallDesc("gettimeofday", unimplementedFunc),
/* 117 */ SyscallDesc("getrusage", unimplementedFunc); /* 117 */ SyscallDesc("getrusage", unimplementedFunc),
/* 118 */ SyscallDesc("getsockopt", unimplementedFunc); /* 118 */ SyscallDesc("getsockopt", unimplementedFunc),
/* 119 */ SyscallDesc("getcwd", unimplementedFunc); /* 119 */ SyscallDesc("getcwd", unimplementedFunc),
/* 120 */ SyscallDesc("readv", unimplementedFunc); /* 120 */ SyscallDesc("readv", unimplementedFunc),
/* 121 */ SyscallDesc("writev", unimplementedFunc); /* 121 */ SyscallDesc("writev", unimplementedFunc),
/* 122 */ SyscallDesc("settimeofday", unimplementedFunc); /* 122 */ SyscallDesc("settimeofday", unimplementedFunc),
/* 123 */ SyscallDesc("fchown", unimplementedFunc); /* 123 */ SyscallDesc("fchown", unimplementedFunc),
/* 124 */ SyscallDesc("fchmod", unimplementedFunc); /* 124 */ SyscallDesc("fchmod", unimplementedFunc),
/* 125 */ SyscallDesc("recvfrom", unimplementedFunc); /* 125 */ SyscallDesc("recvfrom", unimplementedFunc),
/* 126 */ SyscallDesc("setreuid", unimplementedFunc); /* 126 */ SyscallDesc("setreuid", unimplementedFunc),
/* 127 */ SyscallDesc("setregid", unimplementedFunc); /* 127 */ SyscallDesc("setregid", unimplementedFunc),
/* 128 */ SyscallDesc("rename", unimplementedFunc); /* 128 */ SyscallDesc("rename", unimplementedFunc),
/* 129 */ SyscallDesc("truncate", unimplementedFunc); /* 129 */ SyscallDesc("truncate", unimplementedFunc),
/* 130 */ SyscallDesc("ftruncate", unimplementedFunc); /* 130 */ SyscallDesc("ftruncate", unimplementedFunc),
/* 131 */ SyscallDesc("flock", unimplementedFunc); /* 131 */ SyscallDesc("flock", unimplementedFunc),
/* 132 */ SyscallDesc("lstat64", unimplementedFunc); /* 132 */ SyscallDesc("lstat64", unimplementedFunc),
/* 133 */ SyscallDesc("sendto", unimplementedFunc); /* 133 */ SyscallDesc("sendto", unimplementedFunc),
/* 134 */ SyscallDesc("shutdown", unimplementedFunc); /* 134 */ SyscallDesc("shutdown", unimplementedFunc),
/* 135 */ SyscallDesc("socketpair", unimplementedFunc); /* 135 */ SyscallDesc("socketpair", unimplementedFunc),
/* 136 */ SyscallDesc("mkdir", unimplementedFunc); /* 136 */ SyscallDesc("mkdir", unimplementedFunc),
/* 137 */ SyscallDesc("rmdir", unimplementedFunc); /* 137 */ SyscallDesc("rmdir", unimplementedFunc),
/* 138 */ SyscallDesc("utimes", unimplementedFunc); /* 138 */ SyscallDesc("utimes", unimplementedFunc),
/* 139 */ SyscallDesc("stat64", unimplementedFunc); /* 139 */ SyscallDesc("stat64", unimplementedFunc),
/* 140 */ SyscallDesc("sendfile64", unimplementedFunc); /* 140 */ SyscallDesc("sendfile64", unimplementedFunc),
/* 141 */ SyscallDesc("getpeername", unimplementedFunc); /* 141 */ SyscallDesc("getpeername", unimplementedFunc),
/* 142 */ SyscallDesc("futex", unimplementedFunc); /* 142 */ SyscallDesc("futex", unimplementedFunc),
/* 143 */ SyscallDesc("gettid", unimplementedFunc); /* 143 */ SyscallDesc("gettid", unimplementedFunc),
/* 144 */ SyscallDesc("getrlimit", unimplementedFunc); /* 144 */ SyscallDesc("getrlimit", unimplementedFunc),
/* 145 */ SyscallDesc("setrlimit", unimplementedFunc); /* 145 */ SyscallDesc("setrlimit", unimplementedFunc),
/* 146 */ SyscallDesc("pivot_root", unimplementedFunc); /* 146 */ SyscallDesc("pivot_root", unimplementedFunc),
/* 147 */ SyscallDesc("prctl", unimplementedFunc); /* 147 */ SyscallDesc("prctl", unimplementedFunc),
/* 148 */ SyscallDesc("pciconfig_read", unimplementedFunc); /* 148 */ SyscallDesc("pciconfig_read", unimplementedFunc),
/* 149 */ SyscallDesc("pciconfig_write", unimplementedFunc); /* 149 */ SyscallDesc("pciconfig_write", unimplementedFunc),
/* 150 */ SyscallDesc("getsockname", unimplementedFunc); /* 150 */ SyscallDesc("getsockname", unimplementedFunc),
/* 151 */ SyscallDesc("inotify_init", unimplementedFunc); /* 151 */ SyscallDesc("inotify_init", unimplementedFunc),
/* 152 */ SyscallDesc("inotify_add_watch", unimplementedFunc); /* 152 */ SyscallDesc("inotify_add_watch", unimplementedFunc),
/* 153 */ SyscallDesc("poll", unimplementedFunc); /* 153 */ SyscallDesc("poll", unimplementedFunc),
/* 154 */ SyscallDesc("getdents64", unimplementedFunc); /* 154 */ SyscallDesc("getdents64", unimplementedFunc),
/* 155 */ SyscallDesc("fcntl64", unimplementedFunc); /* 155 */ SyscallDesc("fcntl64", unimplementedFunc),
/* 156 */ SyscallDesc("inotify_rm_watch", unimplementedFunc); /* 156 */ SyscallDesc("inotify_rm_watch", unimplementedFunc),
/* 157 */ SyscallDesc("statfs", unimplementedFunc); /* 157 */ SyscallDesc("statfs", unimplementedFunc),
/* 158 */ SyscallDesc("fstatfs", unimplementedFunc); /* 158 */ SyscallDesc("fstatfs", unimplementedFunc),
/* 159 */ SyscallDesc("umount", unimplementedFunc); /* 159 */ SyscallDesc("umount", unimplementedFunc),
/* 160 */ SyscallDesc("sched_set_affinity", unimplementedFunc); /* 160 */ SyscallDesc("sched_set_affinity", unimplementedFunc),
/* 161 */ SyscallDesc("sched_get_affinity", unimplementedFunc); /* 161 */ SyscallDesc("sched_get_affinity", unimplementedFunc),
/* 162 */ SyscallDesc("getdomainname", unimplementedFunc); /* 162 */ SyscallDesc("getdomainname", unimplementedFunc),
/* 163 */ SyscallDesc("setdomainname", unimplementedFunc); /* 163 */ SyscallDesc("setdomainname", unimplementedFunc),
/* 164 */ SyscallDesc("utrap_install", unimplementedFunc); /* 164 */ SyscallDesc("utrap_install", unimplementedFunc),
/* 165 */ SyscallDesc("quotactl", unimplementedFunc); /* 165 */ SyscallDesc("quotactl", unimplementedFunc),
/* 166 */ SyscallDesc("set_tid_address", unimplementedFunc); /* 166 */ SyscallDesc("set_tid_address", unimplementedFunc),
/* 167 */ SyscallDesc("mount", unimplementedFunc); /* 167 */ SyscallDesc("mount", unimplementedFunc),
/* 168 */ SyscallDesc("ustat", unimplementedFunc); /* 168 */ SyscallDesc("ustat", unimplementedFunc),
/* 169 */ SyscallDesc("setxattr", unimplementedFunc); /* 169 */ SyscallDesc("setxattr", unimplementedFunc),
/* 170 */ SyscallDesc("lsetxattr", unimplementedFunc); /* 170 */ SyscallDesc("lsetxattr", unimplementedFunc),
/* 171 */ SyscallDesc("fsetxattr", unimplementedFunc); /* 171 */ SyscallDesc("fsetxattr", unimplementedFunc),
/* 172 */ SyscallDesc("getxattr", unimplementedFunc); /* 172 */ SyscallDesc("getxattr", unimplementedFunc),
/* 173 */ SyscallDesc("lgetxattr", unimplementedFunc); /* 173 */ SyscallDesc("lgetxattr", unimplementedFunc),
/* 174 */ SyscallDesc("getdents", unimplementedFunc); /* 174 */ SyscallDesc("getdents", unimplementedFunc),
/* 175 */ SyscallDesc("setsid", unimplementedFunc); /* 175 */ SyscallDesc("setsid", unimplementedFunc),
/* 176 */ SyscallDesc("fchdir", unimplementedFunc); /* 176 */ SyscallDesc("fchdir", unimplementedFunc),
/* 177 */ SyscallDesc("fgetxattr", unimplementedFunc); /* 177 */ SyscallDesc("fgetxattr", unimplementedFunc),
/* 178 */ SyscallDesc("listxattr", unimplementedFunc); /* 178 */ SyscallDesc("listxattr", unimplementedFunc),
/* 179 */ SyscallDesc("llistxattr", unimplementedFunc); /* 179 */ SyscallDesc("llistxattr", unimplementedFunc),
/* 180 */ SyscallDesc("flistxattr", unimplementedFunc); /* 180 */ SyscallDesc("flistxattr", unimplementedFunc),
/* 181 */ SyscallDesc("removexattr", unimplementedFunc); /* 181 */ SyscallDesc("removexattr", unimplementedFunc),
/* 182 */ SyscallDesc("lremovexattr", unimplementedFunc); /* 182 */ SyscallDesc("lremovexattr", unimplementedFunc),
/* 183 */ SyscallDesc("sigpending", unimplementedFunc); /* 183 */ SyscallDesc("sigpending", unimplementedFunc),
/* 184 */ SyscallDesc("query_module", unimplementedFunc); /* 184 */ SyscallDesc("query_module", unimplementedFunc),
/* 185 */ SyscallDesc("setpgid", unimplementedFunc); /* 185 */ SyscallDesc("setpgid", unimplementedFunc),
/* 186 */ SyscallDesc("fremovexattr", unimplementedFunc); /* 186 */ SyscallDesc("fremovexattr", unimplementedFunc),
/* 187 */ SyscallDesc("tkill", unimplementedFunc); /* 187 */ SyscallDesc("tkill", unimplementedFunc),
/* 188 */ SyscallDesc("exit_group", unimplementedFunc); /* 188 */ SyscallDesc("exit_group", unimplementedFunc),
/* 189 */ SyscallDesc("uname", unameFunc); /* 189 */ SyscallDesc("uname", unameFunc),
/* 190 */ SyscallDesc("init_module", unimplementedFunc); /* 190 */ SyscallDesc("init_module", unimplementedFunc),
/* 191 */ SyscallDesc("personality", unimplementedFunc); /* 191 */ SyscallDesc("personality", unimplementedFunc),
/* 192 */ SyscallDesc("remap_file_pages", unimplementedFunc); /* 192 */ SyscallDesc("remap_file_pages", unimplementedFunc),
/* 193 */ SyscallDesc("epoll_create", unimplementedFunc); /* 193 */ SyscallDesc("epoll_create", unimplementedFunc),
/* 194 */ SyscallDesc("epoll_ctl", unimplementedFunc); /* 194 */ SyscallDesc("epoll_ctl", unimplementedFunc),
/* 195 */ SyscallDesc("epoll_wait", unimplementedFunc); /* 195 */ SyscallDesc("epoll_wait", unimplementedFunc),
/* 196 */ SyscallDesc("ioprio_set", unimplementedFunc); /* 196 */ SyscallDesc("ioprio_set", unimplementedFunc),
/* 197 */ SyscallDesc("getppid", getppidFunc); /* 197 */ SyscallDesc("getppid", getppidFunc),
/* 198 */ SyscallDesc("sigaction", unimplementedFunc); /* 198 */ SyscallDesc("sigaction", unimplementedFunc),
/* 199 */ SyscallDesc("sgetmask", unimplementedFunc); /* 199 */ SyscallDesc("sgetmask", unimplementedFunc),
/* 200 */ SyscallDesc("ssetmask", unimplementedFunc); /* 200 */ SyscallDesc("ssetmask", unimplementedFunc),
/* 201 */ SyscallDesc("sigsuspend", unimplementedFunc); /* 201 */ SyscallDesc("sigsuspend", unimplementedFunc),
/* 202 */ SyscallDesc("oldlstat", unimplementedFunc); /* 202 */ SyscallDesc("oldlstat", unimplementedFunc),
/* 203 */ SyscallDesc("uselib", unimplementedFunc); /* 203 */ SyscallDesc("uselib", unimplementedFunc),
/* 204 */ SyscallDesc("readdir", unimplementedFunc); /* 204 */ SyscallDesc("readdir", unimplementedFunc),
/* 205 */ SyscallDesc("readahead", unimplementedFunc); /* 205 */ SyscallDesc("readahead", unimplementedFunc),
/* 206 */ SyscallDesc("socketcall", unimplementedFunc); /* 206 */ SyscallDesc("socketcall", unimplementedFunc),
/* 207 */ SyscallDesc("syslog", unimplementedFunc); /* 207 */ SyscallDesc("syslog", unimplementedFunc),
/* 208 */ SyscallDesc("lookup_dcookie", unimplementedFunc); /* 208 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
/* 209 */ SyscallDesc("fadvise64", unimplementedFunc); /* 209 */ SyscallDesc("fadvise64", unimplementedFunc),
/* 210 */ SyscallDesc("fadvise64_64", unimplementedFunc); /* 210 */ SyscallDesc("fadvise64_64", unimplementedFunc),
/* 211 */ SyscallDesc("tgkill", unimplementedFunc); /* 211 */ SyscallDesc("tgkill", unimplementedFunc),
/* 212 */ SyscallDesc("waitpid", unimplementedFunc); /* 212 */ SyscallDesc("waitpid", unimplementedFunc),
/* 213 */ SyscallDesc("swapoff", unimplementedFunc); /* 213 */ SyscallDesc("swapoff", unimplementedFunc),
/* 214 */ SyscallDesc("sysinfo", unimplementedFunc); /* 214 */ SyscallDesc("sysinfo", unimplementedFunc),
/* 215 */ SyscallDesc("ipc", unimplementedFunc); /* 215 */ SyscallDesc("ipc", unimplementedFunc),
/* 216 */ SyscallDesc("sigreturn", unimplementedFunc); /* 216 */ SyscallDesc("sigreturn", unimplementedFunc),
/* 217 */ SyscallDesc("clone", unimplementedFunc); /* 217 */ SyscallDesc("clone", unimplementedFunc),
/* 218 */ SyscallDesc("ioprio_get", unimplementedFunc); /* 218 */ SyscallDesc("ioprio_get", unimplementedFunc),
/* 219 */ SyscallDesc("adjtimex", unimplementedFunc); /* 219 */ SyscallDesc("adjtimex", unimplementedFunc),
/* 220 */ SyscallDesc("sigprocmask", unimplementedFunc); /* 220 */ SyscallDesc("sigprocmask", unimplementedFunc),
/* 221 */ SyscallDesc("create_module", unimplementedFunc); /* 221 */ SyscallDesc("create_module", unimplementedFunc),
/* 222 */ SyscallDesc("delete_module", unimplementedFunc); /* 222 */ SyscallDesc("delete_module", unimplementedFunc),
/* 223 */ SyscallDesc("get_kernel_syms", unimplementedFunc); /* 223 */ SyscallDesc("get_kernel_syms", unimplementedFunc),
/* 224 */ SyscallDesc("getpgid", unimplementedFunc); /* 224 */ SyscallDesc("getpgid", unimplementedFunc),
/* 225 */ SyscallDesc("bdflush", unimplementedFunc); /* 225 */ SyscallDesc("bdflush", unimplementedFunc),
/* 226 */ SyscallDesc("sysfs", unimplementedFunc); /* 226 */ SyscallDesc("sysfs", unimplementedFunc),
/* 227 */ SyscallDesc("afs_syscall", unimplementedFunc); /* 227 */ SyscallDesc("afs_syscall", unimplementedFunc),
/* 228 */ SyscallDesc("setfsuid", unimplementedFunc); /* 228 */ SyscallDesc("setfsuid", unimplementedFunc),
/* 229 */ SyscallDesc("setfsgid", unimplementedFunc); /* 229 */ SyscallDesc("setfsgid", unimplementedFunc),
/* 230 */ SyscallDesc("_newselect", unimplementedFunc); /* 230 */ SyscallDesc("_newselect", unimplementedFunc),
/* 231 */ SyscallDesc("time", unimplementedFunc); /* 231 */ SyscallDesc("time", unimplementedFunc),
/* 232 */ SyscallDesc("oldstat", unimplementedFunc); /* 232 */ SyscallDesc("oldstat", unimplementedFunc),
/* 233 */ SyscallDesc("stime", unimplementedFunc); /* 233 */ SyscallDesc("stime", unimplementedFunc),
/* 234 */ SyscallDesc("statfs64", unimplementedFunc); /* 234 */ SyscallDesc("statfs64", unimplementedFunc),
/* 235 */ SyscallDesc("fstatfs64", unimplementedFunc); /* 235 */ SyscallDesc("fstatfs64", unimplementedFunc),
/* 236 */ SyscallDesc("_llseek", unimplementedFunc); /* 236 */ SyscallDesc("_llseek", unimplementedFunc),
/* 237 */ SyscallDesc("mlock", unimplementedFunc); /* 237 */ SyscallDesc("mlock", unimplementedFunc),
/* 238 */ SyscallDesc("munlock", unimplementedFunc); /* 238 */ SyscallDesc("munlock", unimplementedFunc),
/* 239 */ SyscallDesc("mlockall", unimplementedFunc); /* 239 */ SyscallDesc("mlockall", unimplementedFunc),
/* 240 */ SyscallDesc("munlockall", unimplementedFunc); /* 240 */ SyscallDesc("munlockall", unimplementedFunc),
/* 241 */ SyscallDesc("sched_setparam", unimplementedFunc); /* 241 */ SyscallDesc("sched_setparam", unimplementedFunc),
/* 242 */ SyscallDesc("sched_getparam", unimplementedFunc); /* 242 */ SyscallDesc("sched_getparam", unimplementedFunc),
/* 243 */ SyscallDesc("sched_setscheduler", unimplementedFunc); /* 243 */ SyscallDesc("sched_setscheduler", unimplementedFunc),
/* 244 */ SyscallDesc("sched_getscheduler", unimplementedFunc); /* 244 */ SyscallDesc("sched_getscheduler", unimplementedFunc),
/* 245 */ SyscallDesc("sched_yield", unimplementedFunc); /* 245 */ SyscallDesc("sched_yield", unimplementedFunc),
/* 246 */ SyscallDesc("sched_get_priority_max", unimplimented); /* 246 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
/* 247 */ SyscallDesc("sched_get_priority_min", unimplimented); /* 247 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
/* 248 */ SyscallDesc("sched_rr_get_interval", unimplimented); /* 248 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
/* 249 */ SyscallDesc("nanosleep", unimplementedFunc); /* 249 */ SyscallDesc("nanosleep", unimplementedFunc),
/* 250 */ SyscallDesc("mremap", unimplementedFunc); /* 250 */ SyscallDesc("mremap", unimplementedFunc),
/* 251 */ SyscallDesc("_sysctl", unimplementedFunc); /* 251 */ SyscallDesc("_sysctl", unimplementedFunc),
/* 252 */ SyscallDesc("getsid", unimplementedFunc); /* 252 */ SyscallDesc("getsid", unimplementedFunc),
/* 253 */ SyscallDesc("fdatasync", unimplementedFunc); /* 253 */ SyscallDesc("fdatasync", unimplementedFunc),
/* 254 */ SyscallDesc("nfsservctl", unimplementedFunc); /* 254 */ SyscallDesc("nfsservctl", unimplementedFunc),
/* 255 */ SyscallDesc("aplib", unimplementedFunc); /* 255 */ SyscallDesc("aplib", unimplementedFunc),
/* 256 */ SyscallDesc("clock_settime", unimplementedFunc); /* 256 */ SyscallDesc("clock_settime", unimplementedFunc),
/* 257 */ SyscallDesc("clock_gettime", unimplementedFunc); /* 257 */ SyscallDesc("clock_gettime", unimplementedFunc),
/* 258 */ SyscallDesc("clock_getres", unimplementedFunc); /* 258 */ SyscallDesc("clock_getres", unimplementedFunc),
/* 259 */ SyscallDesc("clock_nanosleep", unimplementedFunc); /* 259 */ SyscallDesc("clock_nanosleep", unimplementedFunc),
/* 260 */ SyscallDesc("sched_getaffinity", unimplementedFunc); /* 260 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
/* 261 */ SyscallDesc("sched_setaffinity", unimplementedFunc); /* 261 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
/* 262 */ SyscallDesc("timer_settime", unimplementedFunc); /* 262 */ SyscallDesc("timer_settime", unimplementedFunc),
/* 263 */ SyscallDesc("timer_gettime", unimplementedFunc); /* 263 */ SyscallDesc("timer_gettime", unimplementedFunc),
/* 264 */ SyscallDesc("timer_getoverrun", unimplementedFunc); /* 264 */ SyscallDesc("timer_getoverrun", unimplementedFunc),
/* 265 */ SyscallDesc("timer_delete", unimplementedFunc); /* 265 */ SyscallDesc("timer_delete", unimplementedFunc),
/* 266 */ SyscallDesc("timer_create", unimplementedFunc); /* 266 */ SyscallDesc("timer_create", unimplementedFunc),
/* 267 */ SyscallDesc("vserver", unimplementedFunc); /* 267 */ SyscallDesc("vserver", unimplementedFunc),
/* 268 */ SyscallDesc("io_setup", unimplementedFunc); /* 268 */ SyscallDesc("io_setup", unimplementedFunc),
/* 269 */ SyscallDesc("io_destroy", unimplementedFunc); /* 269 */ SyscallDesc("io_destroy", unimplementedFunc),
/* 270 */ SyscallDesc("io_submit", unimplementedFunc); /* 270 */ SyscallDesc("io_submit", unimplementedFunc),
/* 271 */ SyscallDesc("io_cancel", unimplementedFunc); /* 271 */ SyscallDesc("io_cancel", unimplementedFunc),
/* 272 */ SyscallDesc("io_getevents", unimplementedFunc); /* 272 */ SyscallDesc("io_getevents", unimplementedFunc),
/* 273 */ SyscallDesc("mq_open", unimplementedFunc); /* 273 */ SyscallDesc("mq_open", unimplementedFunc),
/* 274 */ SyscallDesc("mq_unlink", unimplementedFunc); /* 274 */ SyscallDesc("mq_unlink", unimplementedFunc),
/* 275 */ SyscallDesc("mq_timedsend", unimplementedFunc); /* 275 */ SyscallDesc("mq_timedsend", unimplementedFunc),
/* 276 */ SyscallDesc("mq_timedreceive", unimplementedFunc); /* 276 */ SyscallDesc("mq_timedreceive", unimplementedFunc),
/* 277 */ SyscallDesc("mq_notify", unimplementedFunc); /* 277 */ SyscallDesc("mq_notify", unimplementedFunc),
/* 278 */ SyscallDesc("mq_getsetattr", unimplementedFunc); /* 278 */ SyscallDesc("mq_getsetattr", unimplementedFunc),
/* 279 */ SyscallDesc("waitid", unimplementedFunc); /* 279 */ SyscallDesc("waitid", unimplementedFunc),
/* 280 */ SyscallDesc("sys_setaltroot", unimplementedFunc); /* 280 */ SyscallDesc("sys_setaltroot", unimplementedFunc),
/* 281 */ SyscallDesc("add_key", unimplementedFunc); /* 281 */ SyscallDesc("add_key", unimplementedFunc),
/* 282 */ SyscallDesc("request_key", unimplementedFunc); /* 282 */ SyscallDesc("request_key", unimplementedFunc),
/* 283 */ SyscallDesc("keyctl", unimplementedFunc); /* 283 */ SyscallDesc("keyctl", unimplementedFunc)
}; };
SparcLinuxProcess::SparcLinuxProcess(const std::string &name, SparcLinuxProcess::SparcLinuxProcess(const std::string &name,
ObjectFile *objFile, ObjectFile *objFile,
System * system,
int stdin_fd, int stdin_fd,
int stdout_fd, int stdout_fd,
int stderr_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &argv,
std::vector<std::string> &envp) std::vector<std::string> &envp)
: LiveProcess(name, objFile, stdin_fd, stdout_fd, stderr_fd, argv, envp), : LiveProcess(name, objFile, system,
stdin_fd, stdout_fd, stderr_fd, argv, envp),
Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
{ {
// The sparc syscall table must be <= 283 entries because that is all there // The sparc syscall table must be <= 283 entries because that is all there
// is space for. // is space for.
assert(Num_Syscall_Descs <= 283); assert(Num_Syscall_Descs <= 283);
init_regs->intRegFile[0] = 0;
} }
SyscallDesc* SyscallDesc*
AlphaLinuxProcess::getDesc(int callnum) SparcLinuxProcess::getDesc(int callnum)
{ {
if (callnum < 0 || callnum > Num_Syscall_Descs) if (callnum < 0 || callnum > Num_Syscall_Descs)
return NULL; return NULL;

1
arch/sparc/linux/process.hh
View file

@ -39,6 +39,7 @@ class SparcLinuxProcess : public LiveProcess
/// Constructor. /// Constructor.
SparcLinuxProcess(const std::string &name, SparcLinuxProcess(const std::string &name,
ObjectFile *objFile, ObjectFile *objFile,
System * system,
int stdin_fd, int stdout_fd, int stderr_fd, int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &argv,
std::vector<std::string> &envp); std::vector<std::string> &envp);

6
arch/sparc/process.cc
View file

@ -31,11 +31,13 @@
#include "base/loader/object_file.hh" #include "base/loader/object_file.hh"
#include "base/misc.hh" #include "base/misc.hh"
using namespace std;
namespace SparcISA namespace SparcISA
{ {
LiveProcess * LiveProcess *
createProcess(const string &nm, ObjectFile * objFile, createProcess(const string &nm, ObjectFile * objFile, System * system,
int stdin_fd, int stdout_fd, int stderr_fd, int stdin_fd, int stdout_fd, int stderr_fd,
vector<string> &argv, vector<string> &envp) vector<string> &argv, vector<string> &envp)
{ {
@ -44,7 +46,7 @@ createProcess(const string &nm, ObjectFile * objFile,
fatal("Object file does not match architecture."); fatal("Object file does not match architecture.");
switch (objFile->getOpSys()) { switch (objFile->getOpSys()) {
case ObjectFile::Linux: case ObjectFile::Linux:
process = new SparcLinuxProcess(nm, objFile, process = new SparcLinuxProcess(nm, objFile, system,
stdin_fd, stdout_fd, stderr_fd, stdin_fd, stdout_fd, stderr_fd,
argv, envp); argv, envp);
break; break;

2
arch/sparc/process.hh
View file

@ -40,7 +40,7 @@ namespace SparcISA
{ {
LiveProcess * LiveProcess *
createProcess(const std::string &nm, ObjectFile * objFile, createProcess(const std::string &nm, ObjectFile * objFile, System * system,
int stdin_fd, int stdout_fd, int stderr_fd, int stdin_fd, int stdout_fd, int stderr_fd,
std::vector<std::string> &argv, std::vector<std::string> &envp); std::vector<std::string> &argv, std::vector<std::string> &envp);

516
arch/sparc/regfile.hh Normal file
View file

@ -0,0 +1,516 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
#include "arch/sparc/faults.hh"
#include "sim/byteswap.hh"
#include "sim/host.hh"
class Checkpoint;
namespace SparcISA
{
typedef uint8_t RegIndex;
// Maximum trap level
const int MaxTL = 4;
//For right now, let's pretend the register file is flat
typedef IntReg IntRegFile[NumIntRegs];
typedef float float32_t;
typedef double float64_t;
//FIXME long double refers to a 10 byte float, rather than a
//16 byte float as required. This data type may have to be emulated.
typedef double float128_t;
class FloatRegFile
{
protected:
//Since the floating point registers overlap each other,
//A generic storage space is used. The float to be returned is
//pulled from the appropriate section of this region.
char regSpace[32 * 64];
static const int SingleWidth = 32;
static const int DoubleWidth = 64;
static const int QuadWidth = 128;
public:
FloatReg readReg(int floatReg, int width)
{
//In each of these cases, we have to copy the value into a temporary
//variable. This is because we may otherwise try to access an
//unaligned portion of memory.
switch(width)
{
case SingleWidth:
float32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, width);
return htog(result32);
case DoubleWidth:
float64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, width);
return htog(result64);
case QuadWidth:
float128_t result128;
memcpy(&result128, regSpace + 4 * floatReg, width);
return htog(result128);
default:
panic("Attempted to read a %d bit floating point register!", width);
}
}
FloatReg readReg(int floatReg)
{
//Use the "natural" width of a single float
return readReg(floatReg, SingleWidth);
}
FloatRegBits readRegBits(int floatReg, int width)
{
//In each of these cases, we have to copy the value into a temporary
//variable. This is because we may otherwise try to access an
//unaligned portion of memory.
switch(width)
{
case SingleWidth:
uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, width);
return htog(result32);
case DoubleWidth:
uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, width);
return htog(result64);
case QuadWidth:
uint64_t result128;
memcpy(&result128, regSpace + 4 * floatReg, width);
return htog(result128);
default:
panic("Attempted to read a %d bit floating point register!", width);
}
}
FloatRegBits readRegBits(int floatReg)
{
//Use the "natural" width of a single float
return readRegBits(floatReg, SingleWidth);
}
Fault setReg(int floatReg, const FloatReg &val, int width)
{
//In each of these cases, we have to copy the value into a temporary
//variable. This is because we may otherwise try to access an
//unaligned portion of memory.
switch(width)
{
case SingleWidth:
uint32_t result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, width);
case DoubleWidth:
uint64_t result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, width);
case QuadWidth:
uint64_t result128 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result128, width);
default:
panic("Attempted to read a %d bit floating point register!", width);
}
return NoFault;
}
Fault setReg(int floatReg, const FloatReg &val)
{
//Use the "natural" width of a single float
return setReg(floatReg, val, SingleWidth);
}
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
//In each of these cases, we have to copy the value into a temporary
//variable. This is because we may otherwise try to access an
//unaligned portion of memory.
switch(width)
{
case SingleWidth:
uint32_t result32 = gtoh((uint32_t)val);
memcpy(regSpace + 4 * floatReg, &result32, width);
case DoubleWidth:
uint64_t result64 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result64, width);
case QuadWidth:
uint64_t result128 = gtoh((uint64_t)val);
memcpy(regSpace + 4 * floatReg, &result128, width);
default:
panic("Attempted to read a %d bit floating point register!", width);
}
return NoFault;
}
Fault setRegBits(int floatReg, const FloatRegBits &val)
{
//Use the "natural" width of a single float
return setReg(floatReg, val, SingleWidth);
}
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
enum MiscRegIndex
{
MISCREG_PSTATE,
MISCREG_PSTATE_AG,
MISCREG_PSTATE_IE,
MISCREG_PSTATE_PRIV,
MISCREG_PSTATE_AM,
MISCREG_PSTATE_PEF,
MISCREG_PSTATE_RED,
MISCREG_PSTATE_MM,
MISCREG_PSTATE_TLE,
MISCREG_PSTATE_CLE,
MISCREG_TBA,
MISCREG_Y,
MISCREG_Y_VALUE,
MISCREG_PIL,
MISCREG_CWP,
MISCREG_TT_BASE,
MISCREG_TT_END = MISCREG_TT_BASE + MaxTL,
MISCREG_CCR,
MISCREG_CCR_ICC,
MISCREG_CCR_ICC_C,
MISCREG_CCR_ICC_V,
MISCREG_CCR_ICC_Z,
MISCREG_CCR_ICC_N,
MISCREG_CCR_XCC,
MISCREG_CCR_XCC_C,
MISCREG_CCR_XCC_V,
MISCREG_CCR_XCC_Z,
MISCREG_CCR_XCC_N,
MISCREG_ASI,
MISCREG_TL,
MISCREG_TPC_BASE,
MISCREG_TPC_END = MISCREG_TPC_BASE + MaxTL,
MISCREG_TNPC_BASE,
MISCREG_TNPC_END = MISCREG_TNPC_BASE + MaxTL,
MISCREG_TSTATE_BASE,
MISCREG_TSTATE_END = MISCREG_TSTATE_BASE + MaxTL,
MISCREG_TSTATE_CWP_BASE,
MISCREG_TSTATE_CWP_END = MISCREG_TSTATE_CWP_BASE + MaxTL,
MISCREG_TSTATE_PSTATE_BASE,
MISCREG_TSTATE_PSTATE_END = MISCREG_TSTATE_PSTATE_BASE + MaxTL,
MISCREG_TSTATE_ASI_BASE,
MISCREG_TSTATE_ASI_END = MISCREG_TSTATE_ASI_BASE + MaxTL,
MISCREG_TSTATE_CCR_BASE,
MISCREG_TSTATE_CCR_END = MISCREG_TSTATE_CCR_BASE + MaxTL,
MISCREG_TICK,
MISCREG_TICK_COUNTER,
MISCREG_TICK_NPT,
MISCREG_CANSAVE,
MISCREG_CANRESTORE,
MISCREG_OTHERWIN,
MISCREG_CLEANWIN,
MISCREG_WSTATE,
MISCREG_WSTATE_NORMAL,
MISCREG_WSTATE_OTHER,
MISCREG_VER,
MISCREG_VER_MAXWIN,
MISCREG_VER_MAXTL,
MISCREG_VER_MASK,
MISCREG_VER_IMPL,
MISCREG_VER_MANUF,
MISCREG_FSR,
MISCREG_FSR_CEXC,
MISCREG_FSR_CEXC_NXC,
MISCREG_FSR_CEXC_DZC,
MISCREG_FSR_CEXC_UFC,
MISCREG_FSR_CEXC_OFC,
MISCREG_FSR_CEXC_NVC,
MISCREG_FSR_AEXC,
MISCREG_FSR_AEXC_NXC,
MISCREG_FSR_AEXC_DZC,
MISCREG_FSR_AEXC_UFC,
MISCREG_FSR_AEXC_OFC,
MISCREG_FSR_AEXC_NVC,
MISCREG_FSR_FCC0,
MISCREG_FSR_QNE,
MISCREG_FSR_FTT,
MISCREG_FSR_VER,
MISCREG_FSR_NS,
MISCREG_FSR_TEM,
MISCREG_FSR_TEM_NXM,
MISCREG_FSR_TEM_DZM,
MISCREG_FSR_TEM_UFM,
MISCREG_FSR_TEM_OFM,
MISCREG_FSR_TEM_NVM,
MISCREG_FSR_RD,
MISCREG_FSR_FCC1,
MISCREG_FSR_FCC2,
MISCREG_FSR_FCC3,
MISCREG_FPRS,
MISCREG_FPRS_DL,
MISCREG_FPRS_DU,
MISCREG_FPRS_FEF,
numMiscRegs
};
// The control registers, broken out into fields
class MiscRegFile
{
private:
union
{
uint16_t pstate; // Process State Register
struct
{
uint16_t ag:1; // Alternate Globals
uint16_t ie:1; // Interrupt enable
uint16_t priv:1; // Privelege mode
uint16_t am:1; // Address mask
uint16_t pef:1; // PSTATE enable floating-point
uint16_t red:1; // RED (reset, error, debug) state
uint16_t mm:2; // Memory Model
uint16_t tle:1; // Trap little-endian
uint16_t cle:1; // Current little-endian
} pstateFields;
};
uint64_t tba; // Trap Base Address
union
{
uint64_t y; // Y (used in obsolete multiplication)
struct
{
uint64_t value:32; // The actual value stored in y
uint64_t :32; // reserved bits
} yFields;
};
uint8_t pil; // Process Interrupt Register
uint8_t cwp; // Current Window Pointer
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
// on the previous level)
union
{
uint8_t ccr; // Condition Code Register
struct
{
union
{
uint8_t icc:4; // 32-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} iccFields;
};
union
{
uint8_t xcc:4; // 64-bit condition codes
struct
{
uint8_t c:1; // Carry
uint8_t v:1; // Overflow
uint8_t z:1; // Zero
uint8_t n:1; // Negative
} xccFields;
};
} ccrFields;
};
uint8_t asi; // Address Space Identifier
uint8_t tl; // Trap Level
uint64_t tpc[MaxTL]; // Trap Program Counter (value from
// previous trap level)
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
// previous trap level)
union
{
uint64_t tstate[MaxTL]; // Trap State
struct
{
//Values are from previous trap level
uint64_t cwp:5; // Current Window Pointer
uint64_t :2; // Reserved bits
uint64_t pstate:10; // Process State
uint64_t :6; // Reserved bits
uint64_t asi:8; // Address Space Identifier
uint64_t ccr:8; // Condition Code Register
} tstateFields[MaxTL];
};
union
{
uint64_t tick; // Hardware clock-tick counter
struct
{
uint64_t counter:63; // Clock-tick count
uint64_t npt:1; // Non-priveleged trap
} tickFields;
};
uint8_t cansave; // Savable windows
uint8_t canrestore; // Restorable windows
uint8_t otherwin; // Other windows
uint8_t cleanwin; // Clean windows
union
{
uint8_t wstate; // Window State
struct
{
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
// register window trap
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
// register window trap
} wstateFields;
};
union
{
uint64_t ver; // Version
struct
{
uint64_t maxwin:5; // Max CWP value
uint64_t :2; // Reserved bits
uint64_t maxtl:8; // Maximum trap level
uint64_t :8; // Reserved bits
uint64_t mask:8; // Processor mask set revision number
uint64_t impl:16; // Implementation identification number
uint64_t manuf:16; // Manufacturer code
} verFields;
};
union
{
uint64_t fsr; // Floating-Point State Register
struct
{
union
{
uint64_t cexc:5; // Current excpetion
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} cexcFields;
};
union
{
uint64_t aexc:5; // Accrued exception
struct
{
uint64_t nxc:1; // Inexact
uint64_t dzc:1; // Divide by zero
uint64_t ufc:1; // Underflow
uint64_t ofc:1; // Overflow
uint64_t nvc:1; // Invalid operand
} aexcFields;
};
uint64_t fcc0:2; // Floating-Point condtion codes
uint64_t :1; // Reserved bits
uint64_t qne:1; // Deferred trap queue not empty
// with no queue, it should read 0
uint64_t ftt:3; // Floating-Point trap type
uint64_t ver:3; // Version (of the FPU)
uint64_t :2; // Reserved bits
uint64_t ns:1; // Nonstandard floating point
union
{
uint64_t tem:5; // Trap Enable Mask
struct
{
uint64_t nxm:1; // Inexact
uint64_t dzm:1; // Divide by zero
uint64_t ufm:1; // Underflow
uint64_t ofm:1; // Overflow
uint64_t nvm:1; // Invalid operand
} temFields;
};
uint64_t :2; // Reserved bits
uint64_t rd:2; // Rounding direction
uint64_t fcc1:2; // Floating-Point condition codes
uint64_t fcc2:2; // Floating-Point condition codes
uint64_t fcc3:2; // Floating-Point condition codes
uint64_t :26; // Reserved bits
} fsrFields;
};
union
{
uint8_t fprs; // Floating-Point Register State
struct
{
uint8_t dl:1; // Dirty lower
uint8_t du:1; // Dirty upper
uint8_t fef:1; // FPRS enable floating-Point
} fprsFields;
};
public:
MiscReg readReg(int miscReg);
MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
Fault setReg(int miscReg, const MiscReg &val);
Fault setRegWithEffect(int miscReg, const MiscReg &val,
ExecContext *xc);
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, const std::string & section);
void copyMiscRegs(ExecContext * xc);
};
typedef union
{
IntReg intreg;
FloatReg fpreg;
MiscReg ctrlreg;
} AnyReg;
struct RegFile
{
IntRegFile intRegFile; // (signed) integer register file
FloatRegFile floatRegFile; // floating point register file
MiscRegFile miscRegs; // control register file
Addr pc; // Program Counter
Addr npc; // Next Program Counter
Addr nnpc;
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
} // namespace SparcISA
#endif

4
base/remote_gdb.cc
View file

@ -440,7 +440,7 @@ RemoteGDB::getregs()
#ifdef KGDB_FP_REGS #ifdef KGDB_FP_REGS
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
gdbregs[i + KGDB_REG_F0] = context->readFloatRegInt(i); gdbregs[i + KGDB_REG_F0] = context->readFloatRegBits(i);
} }
#endif #endif
} }
@ -467,7 +467,7 @@ RemoteGDB::setregs()
#ifdef KGDB_FP_REGS #ifdef KGDB_FP_REGS
for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) { for (int i = 0; i < TheISA::NumFloatArchRegs; ++i) {
context->setFloatRegInt(i, gdbregs[i + KGDB_REG_F0]); context->setFloatRegBits(i, gdbregs[i + KGDB_REG_F0]);
} }
#endif #endif
context->setPC(gdbregs[KGDB_REG_PC]); context->setPC(gdbregs[KGDB_REG_PC]);

36
cpu/cpu_exec_context.hh
View file

@ -71,6 +71,8 @@ class CPUExecContext
typedef TheISA::MachInst MachInst; typedef TheISA::MachInst MachInst;
typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg; typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
public: public:
typedef ExecContext::Status Status; typedef ExecContext::Status Status;
@ -375,19 +377,24 @@ class CPUExecContext
return regs.intRegFile[reg_idx]; return regs.intRegFile[reg_idx];
} }
float readFloatRegSingle(int reg_idx) FloatReg readFloatReg(int reg_idx, int width)
{ {
return (float)regs.floatRegFile.d[reg_idx]; return regs.floatRegFile.readReg(reg_idx, width);
} }
double readFloatRegDouble(int reg_idx) FloatReg readFloatReg(int reg_idx)
{ {
return regs.floatRegFile.d[reg_idx]; return regs.floatRegFile.readReg(reg_idx);
} }
uint64_t readFloatRegInt(int reg_idx) FloatRegBits readFloatRegBits(int reg_idx, int width)
{ {
return regs.floatRegFile.q[reg_idx]; return regs.floatRegFile.readRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(int reg_idx)
{
return regs.floatRegFile.readRegBits(reg_idx);
} }
void setIntReg(int reg_idx, uint64_t val) void setIntReg(int reg_idx, uint64_t val)
@ -395,19 +402,24 @@ class CPUExecContext
regs.intRegFile[reg_idx] = val; regs.intRegFile[reg_idx] = val;
} }
void setFloatRegSingle(int reg_idx, float val) void setFloatReg(int reg_idx, FloatReg val, int width)
{ {
regs.floatRegFile.d[reg_idx] = (double)val; regs.floatRegFile.setReg(reg_idx, val, width);
} }
void setFloatRegDouble(int reg_idx, double val) void setFloatReg(int reg_idx, FloatReg val)
{ {
regs.floatRegFile.d[reg_idx] = val; regs.floatRegFile.setReg(reg_idx, val);
} }
void setFloatRegInt(int reg_idx, uint64_t val) void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{ {
regs.floatRegFile.q[reg_idx] = val; regs.floatRegFile.setRegBits(reg_idx, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
regs.floatRegFile.setRegBits(reg_idx, val);
} }
uint64_t readPC() uint64_t readPC()

48
cpu/exec_context.hh
View file

@ -54,6 +54,8 @@ class ExecContext
typedef TheISA::RegFile RegFile; typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst; typedef TheISA::MachInst MachInst;
typedef TheISA::IntReg IntReg; typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg; typedef TheISA::MiscReg MiscReg;
public: public:
@ -165,19 +167,23 @@ class ExecContext
// //
virtual uint64_t readIntReg(int reg_idx) = 0; virtual uint64_t readIntReg(int reg_idx) = 0;
virtual float readFloatRegSingle(int reg_idx) = 0; virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
virtual double readFloatRegDouble(int reg_idx) = 0; virtual FloatReg readFloatReg(int reg_idx) = 0;
virtual uint64_t readFloatRegInt(int reg_idx) = 0; virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
virtual void setIntReg(int reg_idx, uint64_t val) = 0; virtual void setIntReg(int reg_idx, uint64_t val) = 0;
virtual void setFloatRegSingle(int reg_idx, float val) = 0; virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
virtual void setFloatRegDouble(int reg_idx, double val) = 0; virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
virtual void setFloatRegInt(int reg_idx, uint64_t val) = 0; virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
virtual uint64_t readPC() = 0; virtual uint64_t readPC() = 0;
@ -333,26 +339,32 @@ class ProxyExecContext : public ExecContext
uint64_t readIntReg(int reg_idx) uint64_t readIntReg(int reg_idx)
{ return actualXC->readIntReg(reg_idx); } { return actualXC->readIntReg(reg_idx); }
float readFloatRegSingle(int reg_idx) FloatReg readFloatReg(int reg_idx, int width)
{ return actualXC->readFloatRegSingle(reg_idx); } { return actualXC->readFloatReg(reg_idx, width); }
double readFloatRegDouble(int reg_idx) FloatReg readFloatReg(int reg_idx)
{ return actualXC->readFloatRegDouble(reg_idx); } { return actualXC->readFloatReg(reg_idx); }
uint64_t readFloatRegInt(int reg_idx) FloatRegBits readFloatRegBits(int reg_idx, int width)
{ return actualXC->readFloatRegInt(reg_idx); } { return actualXC->readFloatRegBits(reg_idx, width); }
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualXC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val) void setIntReg(int reg_idx, uint64_t val)
{ actualXC->setIntReg(reg_idx, val); } { actualXC->setIntReg(reg_idx, val); }
void setFloatRegSingle(int reg_idx, float val) void setFloatReg(int reg_idx, FloatReg val, int width)
{ actualXC->setFloatRegSingle(reg_idx, val); } { actualXC->setFloatReg(reg_idx, val, width); }
void setFloatRegDouble(int reg_idx, double val) void setFloatReg(int reg_idx, FloatReg val)
{ actualXC->setFloatRegDouble(reg_idx, val); } { actualXC->setFloatReg(reg_idx, val); }
void setFloatRegInt(int reg_idx, uint64_t val) void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{ actualXC->setFloatRegInt(reg_idx, val); } { actualXC->setFloatRegBits(reg_idx, val, width); }
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualXC->setFloatRegBits(reg_idx, val); }
uint64_t readPC() { return actualXC->readPC(); } uint64_t readPC() { return actualXC->readPC(); }

12
cpu/o3/alpha_cpu_impl.hh
View file

@ -175,10 +175,8 @@ AlphaFullCPU<Impl>::copyToXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{ {
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag); renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
this->cpuXC->setFloatRegDouble(i, this->cpuXC->setFloatRegBits(i,
this->regFile.readFloatRegDouble(renamed_reg)); this->regFile.readFloatRegBits(renamed_reg));
this->cpuXC->setFloatRegInt(i,
this->regFile.readFloatRegInt(renamed_reg));
} }
this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag, this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
@ -223,10 +221,8 @@ AlphaFullCPU<Impl>::copyFromXC()
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{ {
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag); renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
this->regFile.setFloatRegDouble(renamed_reg, this->regFile.setFloatRegBits(renamed_reg,
this->cpuXC->readFloatRegDouble(i)); this->cpuXC->readFloatRegBits(i));
this->regFile.setFloatRegInt(renamed_reg,
this->cpuXC->readFloatRegInt(i));
} }
// Then loop through the misc registers. // Then loop through the misc registers.

36
cpu/o3/alpha_dyn_inst.hh
View file

@ -152,19 +152,24 @@ class AlphaDynInst : public BaseDynInst<Impl>
return this->cpu->readIntReg(_srcRegIdx[idx]); return this->cpu->readIntReg(_srcRegIdx[idx]);
} }
float readFloatRegSingle(const StaticInst *si, int idx) FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{ {
return this->cpu->readFloatRegSingle(_srcRegIdx[idx]); return this->cpu->readFloatReg(_srcRegIdx[idx], width);
} }
double readFloatRegDouble(const StaticInst *si, int idx) FloatReg readFloatReg(const StaticInst *si, int idx)
{ {
return this->cpu->readFloatRegDouble(_srcRegIdx[idx]); return this->cpu->readFloatReg(_srcRegIdx[idx]);
} }
uint64_t readFloatRegInt(const StaticInst *si, int idx) FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{ {
return this->cpu->readFloatRegInt(_srcRegIdx[idx]); return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
} }
/** @todo: Make results into arrays so they can handle multiple dest /** @todo: Make results into arrays so they can handle multiple dest
@ -176,21 +181,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
this->instResult.integer = val; this->instResult.integer = val;
} }
void setFloatRegSingle(const StaticInst *si, int idx, float val) void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{ {
this->cpu->setFloatRegSingle(_destRegIdx[idx], val); this->cpu->setFloatReg(_destRegIdx[idx], val, width);
this->instResult.fp = val; this->instResult.fp = val;
} }
void setFloatRegDouble(const StaticInst *si, int idx, double val) void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{ {
this->cpu->setFloatRegDouble(_destRegIdx[idx], val); this->cpu->setFloatReg(_destRegIdx[idx], val);
this->instResult.dbl = val; this->instResult.dbl = val;
} }
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{ {
this->cpu->setFloatRegInt(_destRegIdx[idx], val); this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
this->instResult.integer = val;
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
this->instResult.integer = val; this->instResult.integer = val;
} }

47
cpu/o3/cpu.cc
View file

@ -258,8 +258,7 @@ FullO3CPU<Impl>::init()
// Then loop through the floating point registers. // Then loop through the floating point registers.
for (int i = 0; i < TheISA::NumFloatRegs; ++i) for (int i = 0; i < TheISA::NumFloatRegs; ++i)
{ {
regFile.floatRegFile[i].d = src_xc->readFloatRegDouble(i); regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i))
regFile.floatRegFile[i].q = src_xc->readFloatRegInt(i);
} }
/* /*
// Then loop through the misc registers. // Then loop through the misc registers.
@ -348,24 +347,31 @@ FullO3CPU<Impl>::readIntReg(int reg_idx)
} }
template <class Impl> template <class Impl>
float FloatReg
FullO3CPU<Impl>::readFloatRegSingle(int reg_idx) FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
{ {
return regFile.readFloatRegSingle(reg_idx); return regFile.readFloatReg(reg_idx, width);
} }
template <class Impl> template <class Impl>
double FloatReg
FullO3CPU<Impl>::readFloatRegDouble(int reg_idx) FullO3CPU<Impl>::readFloatReg(int reg_idx)
{ {
return regFile.readFloatRegDouble(reg_idx); return regFile.readFloatReg(reg_idx);
} }
template <class Impl> template <class Impl>
uint64_t FloatRegBits
FullO3CPU<Impl>::readFloatRegInt(int reg_idx) FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
{ {
return regFile.readFloatRegInt(reg_idx); return regFile.readFloatRegBits(reg_idx, width);
}
template <class Impl>
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
{
return regFile.readFloatRegBits(reg_idx);
} }
template <class Impl> template <class Impl>
@ -377,23 +383,30 @@ FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
template <class Impl> template <class Impl>
void void
FullO3CPU<Impl>::setFloatRegSingle(int reg_idx, float val) FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{ {
regFile.setFloatRegSingle(reg_idx, val); regFile.setFloatReg(reg_idx, val, width);
} }
template <class Impl> template <class Impl>
void void
FullO3CPU<Impl>::setFloatRegDouble(int reg_idx, double val) FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
{ {
regFile.setFloatRegDouble(reg_idx, val); regFile.setFloatReg(reg_idx, val);
} }
template <class Impl> template <class Impl>
void void
FullO3CPU<Impl>::setFloatRegInt(int reg_idx, uint64_t val) FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{ {
regFile.setFloatRegInt(reg_idx, val); regFile.setFloatRegBits(reg_idx, val, width);
}
template <class Impl>
void
FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
regFile.setFloatRegBits(reg_idx, val);
} }
template <class Impl> template <class Impl>

16
cpu/o3/cpu.hh
View file

@ -170,19 +170,23 @@ class FullO3CPU : public BaseFullCPU
// //
uint64_t readIntReg(int reg_idx); uint64_t readIntReg(int reg_idx);
float readFloatRegSingle(int reg_idx); FloatReg readFloatReg(int reg_idx);
double readFloatRegDouble(int reg_idx); FloatReg readFloatReg(int reg_idx, int width);
uint64_t readFloatRegInt(int reg_idx); FloatRegBits readFloatRegBits(int reg_idx);
FloatRegBits readFloatRegBits(int reg_idx, int width);
void setIntReg(int reg_idx, uint64_t val); void setIntReg(int reg_idx, uint64_t val);
void setFloatRegSingle(int reg_idx, float val); void setFloatReg(int reg_idx, FloatReg val, int width);
void setFloatRegDouble(int reg_idx, double val); void setFloatReg(int reg_idx, FloatReg val, int width);
void setFloatRegInt(int reg_idx, uint64_t val); void setFloatRegBits(int reg_idx, FloatRegBits val);
void setFloatRegBits(int reg_idx, FloatRegBits val);
uint64_t readPC(); uint64_t readPC();

80
cpu/o3/regfile.hh
View file

@ -89,43 +89,64 @@ class PhysRegFile
return intRegFile[reg_idx]; return intRegFile[reg_idx];
} }
float readFloatRegSingle(PhysRegIndex reg_idx) FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as single, has " FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
"data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
return (float)floatRegFile[reg_idx].d; DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
"data %8.8d\n", int(reg_idx), (double)floatReg);
return floatReg;
} }
double readFloatRegDouble(PhysRegIndex reg_idx) FloatReg readFloatReg(PhysRegIndex reg_idx)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as double, has " FloatReg floatReg = floatRegFile.readReg(reg_idx);
" data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
return floatRegFile[reg_idx].d; DPRINTF(IEW, "RegFile: Access to float register %i, has "
"data %8.8d\n", int(reg_idx), (double)floatReg);
return floatReg;
} }
uint64_t readFloatRegInt(PhysRegIndex reg_idx) FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Access to float register %i as int, has data " FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
"%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
return floatRegFile[reg_idx].q; DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
}
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
DPRINTF(IEW, "RegFile: Access to float register %i as int, "
"has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
return floatRegBits;
} }
void setIntReg(PhysRegIndex reg_idx, uint64_t val) void setIntReg(PhysRegIndex reg_idx, uint64_t val)
@ -138,33 +159,33 @@ class PhysRegFile
intRegFile[reg_idx] = val; intRegFile[reg_idx] = val;
} }
void setFloatRegSingle(PhysRegIndex reg_idx, float val) void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), val); int(reg_idx), (double)val);
floatRegFile[reg_idx].d = (double)val; floatRegFile.setReg(reg_idx, val, width);
} }
void setFloatRegDouble(PhysRegIndex reg_idx, double val) void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n", DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), val); int(reg_idx), (double)val);
floatRegFile[reg_idx].d = val; floatRegFile.setReg(reg_idx, val);
} }
void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val) void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
{ {
// Remove the base Float reg dependency. // Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs; reg_idx = reg_idx - numPhysicalIntRegs;
@ -172,9 +193,22 @@ class PhysRegFile
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n", DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), val); int(reg_idx), (uint64_t)val);
floatRegFile[reg_idx].q = val; floatRegFile.setRegBits(reg_idx, val, width);
}
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
{
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), (uint64_t)val);
floatRegFile.setRegBits(reg_idx, val);
} }
uint64_t readPC() uint64_t readPC()

36
cpu/ozone/cpu.hh
View file

@ -406,22 +406,28 @@ class OoOCPU : public BaseCPU
return xc->readIntReg(si->srcRegIdx(idx)); return xc->readIntReg(si->srcRegIdx(idx));
} }
float readFloatRegSingle(StaticInst *si, int idx) FloatReg readFloatReg(StaticInst *si, int idx, width)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegSingle(reg_idx); return xc->readFloatReg(reg_idx, width);
} }
double readFloatRegDouble(StaticInst *si, int idx) FloatReg readFloatReg(StaticInst *si, int idx)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegDouble(reg_idx); return xc->readFloatReg(reg_idx);
} }
uint64_t readFloatRegInt(StaticInst *si, int idx) FloatRegBits readFloatRegBits(StaticInst *si, int idx, int width)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegInt(reg_idx); return xc->readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return xc->readFloatRegBits(reg_idx);
} }
void setIntReg(StaticInst *si, int idx, uint64_t val) void setIntReg(StaticInst *si, int idx, uint64_t val)
@ -429,22 +435,28 @@ class OoOCPU : public BaseCPU
xc->setIntReg(si->destRegIdx(idx), val); xc->setIntReg(si->destRegIdx(idx), val);
} }
void setFloatRegSingle(StaticInst *si, int idx, float val) void setFloatReg(StaticInst *si, int idx, FloatReg val, int width)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegSingle(reg_idx, val); xc->setFloatReg(reg_idx, val, width);
} }
void setFloatRegDouble(StaticInst *si, int idx, double val) void setFloatReg(StaticInst *si, int idx, FloatReg val)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegDouble(reg_idx, val); xc->setFloatReg(reg_idx, val);
} }
void setFloatRegInt(StaticInst *si, int idx, uint64_t val) void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val, int width)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegInt(reg_idx, val); xc->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
xc->setFloatRegBits(reg_idx, val);
} }
uint64_t readPC() { return PC; } uint64_t readPC() { return PC; }

2
cpu/simple/cpu.cc
View file

@ -941,7 +941,7 @@ SimpleCPU::tick()
// maintain $r0 semantics // maintain $r0 semantics
cpuXC->setIntReg(ZeroReg, 0); cpuXC->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA #if THE_ISA == ALPHA_ISA
cpuXC->setFloatRegDouble(ZeroReg, 0.0); cpuXC->setFloatReg(ZeroReg, 0.0);
#endif // ALPHA_ISA #endif // ALPHA_ISA
if (status() == IcacheAccessComplete) { if (status() == IcacheAccessComplete) {

39
cpu/simple/cpu.hh
View file

@ -79,6 +79,8 @@ class SimpleCPU : public BaseCPU
protected: protected:
typedef TheISA::MachInst MachInst; typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg; typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
class CpuPort : public Port class CpuPort : public Port
{ {
@ -321,22 +323,28 @@ class SimpleCPU : public BaseCPU
return cpuXC->readIntReg(si->srcRegIdx(idx)); return cpuXC->readIntReg(si->srcRegIdx(idx));
} }
float readFloatRegSingle(const StaticInst *si, int idx) FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegSingle(reg_idx); return cpuXC->readFloatReg(reg_idx, width);
} }
double readFloatRegDouble(const StaticInst *si, int idx) FloatReg readFloatReg(const StaticInst *si, int idx)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegDouble(reg_idx); return cpuXC->readFloatReg(reg_idx);
} }
uint64_t readFloatRegInt(const StaticInst *si, int idx) FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{ {
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegInt(reg_idx); return cpuXC->readFloatRegBits(reg_idx, width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return cpuXC->readFloatRegBits(reg_idx);
} }
void setIntReg(const StaticInst *si, int idx, uint64_t val) void setIntReg(const StaticInst *si, int idx, uint64_t val)
@ -344,22 +352,29 @@ class SimpleCPU : public BaseCPU
cpuXC->setIntReg(si->destRegIdx(idx), val); cpuXC->setIntReg(si->destRegIdx(idx), val);
} }
void setFloatRegSingle(const StaticInst *si, int idx, float val) void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegSingle(reg_idx, val); cpuXC->setFloatReg(reg_idx, val, width);
} }
void setFloatRegDouble(const StaticInst *si, int idx, double val) void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegDouble(reg_idx, val); cpuXC->setFloatReg(reg_idx, val);
} }
void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{ {
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegInt(reg_idx, val); cpuXC->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegBits(reg_idx, val);
} }
uint64_t readPC() { return cpuXC->readPC(); } uint64_t readPC() { return cpuXC->readPC(); }

2
kern/tru64/tru64.hh
View file

@ -738,7 +738,7 @@ class Tru64 {
for (int i = 0; i < 31; ++i) { for (int i = 0; i < 31; ++i) {
xc->setIntReg(i, htog(sc->sc_regs[i])); xc->setIntReg(i, htog(sc->sc_regs[i]));
xc->setFloatRegInt(i, htog(sc->sc_fpregs[i])); xc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
} }
xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr)); xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));