ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.
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@ -94,12 +94,14 @@ def operands {{
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maybePCRead, maybeIWPCWrite),
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maybePCRead, maybeIWPCWrite),
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'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
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'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
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maybePCRead, maybeAIWPCWrite),
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maybePCRead, maybeAIWPCWrite),
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'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
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'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
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'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
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maybeAlignedPCRead, maybePCWrite),
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maybeAlignedPCRead, maybePCWrite),
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'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
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'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
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maybePCRead, maybePCWrite),
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maybePCRead, maybePCWrite),
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'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
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'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
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maybePCRead, maybePCWrite),
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maybePCRead, maybePCWrite),
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'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
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'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
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'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
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maybePCRead, maybePCWrite),
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maybePCRead, maybePCWrite),
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'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
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'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
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