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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse source 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
This commit is contained in:
Gabe Black 2006-10-27 02:34:26 -04:00
commit f985b752d3
21 changed files with 559 additions and 392 deletions
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2
src/arch/isa_parser.py
View file

@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand):
def makeWrite(self): def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'): if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP') error(0, 'Attempt to write control register as FP')
wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name) wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \ wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name self.base_name
return wb return wb

163
src/arch/sparc/faults.cc
View file

@ -29,15 +29,22 @@
* Kevin Lim * Kevin Lim
*/ */
#include <algorithm>
#include "arch/sparc/faults.hh" #include "arch/sparc/faults.hh"
#include "cpu/thread_context.hh" #include "arch/sparc/isa_traits.hh"
#include "cpu/base.hh" #include "arch/sparc/process.hh"
#include "base/bitfield.hh"
#include "base/trace.hh" #include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM #if !FULL_SYSTEM
#include "sim/process.hh"
#include "mem/page_table.hh" #include "mem/page_table.hh"
#include "sim/process.hh"
#endif #endif
using namespace std;
namespace SparcISA namespace SparcISA
{ {
@ -229,6 +236,121 @@ FaultPriority PageTableFault::_priority = 0;
FaultStat PageTableFault::_count; FaultStat PageTableFault::_count;
#endif #endif
/**
* This sets everything up for a normal trap except for actually jumping to
* the handler. It will need to be expanded to include the state machine in
* the manual. Right now it assumes that traps will always be to the
* privileged level.
*/
void doNormalFault(ThreadContext *tc, TrapType tt)
{
uint64_t TL = tc->readMiscReg(MISCREG_TL);
uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
uint64_t GL = tc->readMiscReg(MISCREG_GL);
uint64_t PC = tc->readPC();
uint64_t NPC = tc->readNextPC();
//Increment the trap level
TL++;
tc->setMiscReg(MISCREG_TL, TL);
//Save off state
//set TSTATE.gl to gl
replaceBits(TSTATE, 42, 40, GL);
//set TSTATE.ccr to ccr
replaceBits(TSTATE, 39, 32, CCR);
//set TSTATE.asi to asi
replaceBits(TSTATE, 31, 24, ASI);
//set TSTATE.pstate to pstate
replaceBits(TSTATE, 20, 8, PSTATE);
//set TSTATE.cwp to cwp
replaceBits(TSTATE, 4, 0, CWP);
//Write back TSTATE
tc->setMiscReg(MISCREG_TSTATE, TSTATE);
//set TPC to PC
tc->setMiscReg(MISCREG_TPC, PC);
//set TNPC to NPC
tc->setMiscReg(MISCREG_TNPC, NPC);
//set HTSTATE.hpstate to hpstate
tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
//TT = trap type;
tc->setMiscReg(MISCREG_TT, tt);
//Update the global register level
if(1/*We're delivering the trap in priveleged mode*/)
tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
else
tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
//PSTATE.mm is unchanged
//PSTATE.pef = whether or not an fpu is present
//XXX We'll say there's one present, even though there aren't
//implementations for a decent number of the instructions
PSTATE |= (1 << 4);
//PSTATE.am = 0
PSTATE &= ~(1 << 3);
if(1/*We're delivering the trap in priveleged mode*/)
{
//PSTATE.priv = 1
PSTATE |= (1 << 2);
//PSTATE.cle = PSTATE.tle
replaceBits(PSTATE, 9, 9, PSTATE >> 8);
}
else
{
//PSTATE.priv = 0
PSTATE &= ~(1 << 2);
//PSTATE.cle = 0
PSTATE &= ~(1 << 9);
}
//PSTATE.ie = 0
PSTATE &= ~(1 << 1);
//PSTATE.tle is unchanged
//PSTATE.tct = 0
//XXX Where exactly is this field?
tc->setMiscReg(MISCREG_PSTATE, PSTATE);
if(0/*We're delivering the trap in hyperprivileged mode*/)
{
//HPSTATE.red = 0
HPSTATE &= ~(1 << 5);
//HPSTATE.hpriv = 1
HPSTATE |= (1 << 2);
//HPSTATE.ibe = 0
HPSTATE &= ~(1 << 10);
//HPSTATE.tlz is unchanged
tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
}
bool changedCWP = true;
if(tt == 0x24)
CWP++;
else if(0x80 <= tt && tt <= 0xbf)
CWP += (CANSAVE + 2);
else if(0xc0 <= tt && tt <= 0xff)
CWP--;
else
changedCWP = false;
if(changedCWP)
{
CWP = (CWP + NWindows) % NWindows;
tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
}
}
#if FULL_SYSTEM #if FULL_SYSTEM
void SparcFault::invoke(ThreadContext * tc) void SparcFault::invoke(ThreadContext * tc)
@ -263,6 +385,40 @@ void TrapInstruction::invoke(ThreadContext * tc)
// Should be handled in ISA. // Should be handled in ISA.
} }
void SpillNNormal::invoke(ThreadContext *tc)
{
doNormalFault(tc, trapType());
Process *p = tc->getProcessPtr();
//This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
//Then adjust the PC and NPC
Addr spillStart = lp->readSpillStart();
tc->setPC(spillStart);
tc->setNextPC(spillStart + sizeof(MachInst));
tc->setNextNPC(spillStart + 2*sizeof(MachInst));
}
void FillNNormal::invoke(ThreadContext *tc)
{
doNormalFault(tc, trapType());
Process * p = tc->getProcessPtr();
//This will only work in faults from a SparcLiveProcess
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
assert(lp);
//The adjust the PC and NPC
Addr fillStart = lp->readFillStart();
tc->setPC(fillStart);
tc->setNextPC(fillStart + sizeof(MachInst));
tc->setNextNPC(fillStart + 2*sizeof(MachInst));
}
void PageTableFault::invoke(ThreadContext *tc) void PageTableFault::invoke(ThreadContext *tc)
{ {
Process *p = tc->getProcessPtr(); Process *p = tc->getProcessPtr();
@ -282,6 +438,7 @@ void PageTableFault::invoke(ThreadContext *tc)
FaultBase::invoke(tc); FaultBase::invoke(tc);
} }
} }
#endif #endif
} // namespace SparcISA } // namespace SparcISA

6
src/arch/sparc/faults.hh
View file

@ -39,8 +39,8 @@
namespace SparcISA namespace SparcISA
{ {
typedef const uint32_t TrapType; typedef uint32_t TrapType;
typedef const uint32_t FaultPriority; typedef uint32_t FaultPriority;
class SparcFault : public FaultBase class SparcFault : public FaultBase
{ {
@ -547,6 +547,7 @@ class SpillNNormal : public EnumeratedFault
FaultName name() {return _name;} FaultName name() {return _name;}
FaultPriority priority() {return _priority;} FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;} FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc);
}; };
class SpillNOther : public EnumeratedFault class SpillNOther : public EnumeratedFault
@ -577,6 +578,7 @@ class FillNNormal : public EnumeratedFault
FaultName name() {return _name;} FaultName name() {return _name;}
FaultPriority priority() {return _priority;} FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;} FaultStat & countStat() {return _count;}
void invoke(ThreadContext * tc);
}; };
class FillNOther : public EnumeratedFault class FillNOther : public EnumeratedFault

2
src/arch/sparc/isa/bitfields.isa
View file

@ -50,7 +50,7 @@ def bitfield D16LO <13:0>;
def bitfield DISP19 <18:0>; def bitfield DISP19 <18:0>;
def bitfield DISP22 <21:0>; def bitfield DISP22 <21:0>;
def bitfield DISP30 <29:0>; def bitfield DISP30 <29:0>;
def bitfield FCN <29:26>; def bitfield FCN <29:25>;
def bitfield I <13>; def bitfield I <13>;
def bitfield IMM_ASI <12:5>; def bitfield IMM_ASI <12:5>;
def bitfield IMM22 <21:0>; def bitfield IMM22 <21:0>;

75
src/arch/sparc/isa/decoder.isa
View file

@ -357,13 +357,9 @@ decode OP default Unknown::unknown()
}}); }});
} }
0x29: HPriv::rdhpr({{ 0x29: HPriv::rdhpr({{
// XXX Need to protect with format that traps non-priv/priv
// access
Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault); Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
}}); }});
0x2A: Priv::rdpr({{ 0x2A: Priv::rdpr({{
// XXX Need to protect with format that traps non-priv
// access
Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault); Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
}}); }});
0x2B: BasicOperate::flushw({{ 0x2B: BasicOperate::flushw({{
@ -425,18 +421,34 @@ decode OP default Unknown::unknown()
xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13); xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
}}); }});
0x31: decode FCN { 0x31: decode FCN {
0x0: BasicOperate::saved({{/*Boogy Boogy*/}}); 0x0: Priv::saved({{
0x1: BasicOperate::restored({{/*Boogy Boogy*/}}); assert(Cansave < NWindows - 2);
assert(Otherwin || Canrestore);
Cansave = Cansave + 1;
if(Otherwin == 0)
Canrestore = Canrestore - 1;
else
Otherwin = Otherwin - 1;
}});
0x1: BasicOperate::restored({{
assert(Cansave || Otherwin);
assert(Canrestore < NWindows - 2);
Canrestore = Canrestore + 1;
if(Otherwin == 0)
Cansave = Cansave - 1;
else
Otherwin = Otherwin - 1;
}});
} }
0x32: Priv::wrpr({{ 0x32: Priv::wrpr({{
// XXX Need to protect with format that traps non-priv // XXX Need to protect with format that traps non-priv
// access // access
fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13); xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
}}); }});
0x33: HPriv::wrhpr({{ 0x33: HPriv::wrhpr({{
// XXX Need to protect with format that traps non-priv/priv // XXX Need to protect with format that traps non-priv/priv
// access // access
fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13); xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
}}); }});
0x34: decode OPF{ 0x34: decode OPF{
format BasicOperate{ format BasicOperate{
@ -684,10 +696,6 @@ decode OP default Unknown::unknown()
NNPC = target; NNPC = target;
if(fault == NoFault) if(fault == NoFault)
{ {
//CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0) if(Canrestore == 0)
{ {
if(Otherwin) if(Otherwin)
@ -697,14 +705,17 @@ decode OP default Unknown::unknown()
} }
else else
{ {
Rd = Rs1 + Rs2_or_imm13; //CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
Cwp = (Cwp - 1 + NWindows) % NWindows;
Cansave = Cansave + 1; Cansave = Cansave + 1;
Canrestore = Canrestore - 1; Canrestore = Canrestore - 1;
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
} }
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
} }
}}); }});
0x3A: decode CC 0x3A: decode CC
@ -747,11 +758,11 @@ decode OP default Unknown::unknown()
fault = new SpillNOther(Wstate<5:3>); fault = new SpillNOther(Wstate<5:3>);
else else
fault = new SpillNNormal(Wstate<2:0>); fault = new SpillNNormal(Wstate<2:0>);
Cwp = (Cwp + 2) % NWindows; //Cwp = (Cwp + 2) % NWindows;
} }
else if(Cleanwin - Canrestore == 0) else if(Cleanwin - Canrestore == 0)
{ {
Cwp = (Cwp + 1) % NWindows; //Cwp = (Cwp + 1) % NWindows;
fault = new CleanWindow; fault = new CleanWindow;
} }
else else
@ -760,17 +771,13 @@ decode OP default Unknown::unknown()
Rd = Rs1 + Rs2_or_imm13; Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave - 1; Cansave = Cansave - 1;
Canrestore = Canrestore + 1; Canrestore = Canrestore + 1;
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
} }
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}}); }});
0x3D: restore({{ 0x3D: restore({{
//CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
Cwp = (Cwp - 1 + NWindows) % NWindows;
if(Canrestore == 0) if(Canrestore == 0)
{ {
if(Otherwin) if(Otherwin)
@ -780,14 +787,18 @@ decode OP default Unknown::unknown()
} }
else else
{ {
//CWP should be set directly so that it always happens
//Also, this will allow writing to the new window and
//reading from the old one
Cwp = (Cwp - 1 + NWindows) % NWindows;
Rd = Rs1 + Rs2_or_imm13; Rd = Rs1 + Rs2_or_imm13;
Cansave = Cansave + 1; Cansave = Cansave + 1;
Canrestore = Canrestore - 1; Canrestore = Canrestore - 1;
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
} }
//This is here to make sure the CWP is written
//no matter what. This ensures that the results
//are written in the new window as well.
xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
}}); }});
0x3E: decode FCN { 0x3E: decode FCN {
0x0: Priv::done({{ 0x0: Priv::done({{
@ -812,7 +823,7 @@ decode OP default Unknown::unknown()
Ccr = Tstate<39:32>; Ccr = Tstate<39:32>;
Gl = Tstate<42:40>; Gl = Tstate<42:40>;
NPC = Tpc; NPC = Tpc;
NNPC = Tnpc + 4; NNPC = Tnpc;
Tl = Tl - 1; Tl = Tl - 1;
}}); }});
} }

5
src/arch/sparc/isa/formats/priv.isa
View file

@ -121,15 +121,14 @@ let {{
// Primary format for integer operate instructions: // Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{ def format Priv(code, *opt_flags) {{
checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) || checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
(header_output, decoder_output, (header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code, exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',)) checkCode, name, Name, opt_flags + ('IprAccessOp',))
}}; }};
def format HPriv(code, *opt_flags) {{ def format HPriv(code, *opt_flags) {{
checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)" checkCode = "!Hpstate<2:2>"
(header_output, decoder_output, (header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code, exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',)) checkCode, name, Name, opt_flags + ('IprAccessOp',))

21
src/arch/sparc/isa/operands.isa
View file

@ -95,18 +95,19 @@ def operands {{
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56), 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
# Mem gets a large number so it's always last # Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)

9
src/arch/sparc/isa_traits.hh
View file

@ -57,12 +57,11 @@ namespace SparcISA
//This makes sure the big endian versions of certain functions are used. //This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest; using namespace BigEndianGuest;
// Alpha Does NOT have a delay slot // SPARC have a delay slot
#define ISA_HAS_DELAY_SLOT 1 #define ISA_HAS_DELAY_SLOT 1
//TODO this needs to be a SPARC Noop // SPARC NOP (sethi %(hi(0), g0)
// Alpha UNOP (ldq_u r31,0(r0)) const MachInst NoopMachInst = 0x01000000;
const MachInst NoopMachInst = 0x2ffe0000;
const int NumIntRegs = 32; const int NumIntRegs = 32;
const int NumFloatRegs = 64; const int NumFloatRegs = 64;
@ -87,7 +86,7 @@ namespace SparcISA
const int MaxPGL = 2; const int MaxPGL = 2;
// NWINDOWS - number of register windows, can be 3 to 32 // NWINDOWS - number of register windows, can be 3 to 32
const int NWindows = 32; const int NWindows = 8;
// semantically meaningful register indices // semantically meaningful register indices
const int ZeroReg = 0; // architecturally meaningful const int ZeroReg = 0; // architecturally meaningful

224
src/arch/sparc/miscregfile.cc
View file

@ -202,282 +202,164 @@ MiscReg MiscRegFile::readReg(int miscReg)
} }
} }
MiscReg MiscRegFile::readRegWithEffect(int miscReg, MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
Fault &fault, ThreadContext * tc)
{ {
fault = NoFault;
switch (miscReg) { switch (miscReg) {
case MISCREG_Y:
case MISCREG_CCR:
case MISCREG_ASI:
return readReg(miscReg);
case MISCREG_TICK: case MISCREG_TICK:
case MISCREG_PRIVTICK: case MISCREG_PRIVTICK:
// Check for reading privilege
if (tickFields.npt && !isNonPriv()) {
fault = new PrivilegedAction;
return 0;
}
return tc->getCpuPtr()->curCycle() - tickFields.counter | return tc->getCpuPtr()->curCycle() - tickFields.counter |
tickFields.npt << 63; tickFields.npt << 63;
case MISCREG_PC:
return tc->readPC();
case MISCREG_FPRS: case MISCREG_FPRS:
fault = new UnimpFault("FPU not implemented\n"); panic("FPU not implemented\n");
return 0;
case MISCREG_PCR: case MISCREG_PCR:
fault = new UnimpFault("Performance Instrumentation not impl\n");
return 0;
case MISCREG_PIC: case MISCREG_PIC:
fault = new UnimpFault("Performance Instrumentation not impl\n"); panic("Performance Instrumentation not impl\n");
return 0;
case MISCREG_GSR:
return readReg(miscReg);
/** Privilged Registers */
case MISCREG_TPC:
case MISCREG_TNPC:
case MISCREG_TSTATE:
case MISCREG_TT:
if (tl == 0) {
fault = new IllegalInstruction;
return 0;
} // NOTE THE FALL THROUGH!
case MISCREG_PSTATE:
case MISCREG_TL:
return readReg(miscReg);
case MISCREG_TBA:
return readReg(miscReg) & ULL(~0x7FFF);
case MISCREG_PIL:
case MISCREG_CWP:
case MISCREG_CANSAVE:
case MISCREG_CANRESTORE:
case MISCREG_CLEANWIN:
case MISCREG_OTHERWIN:
case MISCREG_WSTATE:
case MISCREG_GL:
return readReg(miscReg);
/** Floating Point Status Register */ /** Floating Point Status Register */
case MISCREG_FSR: case MISCREG_FSR:
panic("Floating Point not implemented\n"); panic("Floating Point not implemented\n");
default:
#if FULL_SYSTEM
return readFSRegWithEffect(miscReg, fault, tc);
#else
fault = new IllegalInstruction;
return 0;
#endif
} }
return readReg(miscReg);
} }
Fault MiscRegFile::setReg(int miscReg, const MiscReg &val) void MiscRegFile::setReg(int miscReg, const MiscReg &val)
{ {
switch (miscReg) { switch (miscReg) {
case MISCREG_Y: case MISCREG_Y:
y = val; y = val;
return NoFault; break;
case MISCREG_CCR: case MISCREG_CCR:
ccr = val; ccr = val;
return NoFault; break;
case MISCREG_ASI: case MISCREG_ASI:
asi = val; asi = val;
return NoFault; break;
case MISCREG_FPRS: case MISCREG_FPRS:
fprs = val; fprs = val;
return NoFault; break;
case MISCREG_TICK: case MISCREG_TICK:
tick = val; tick = val;
return NoFault; break;
case MISCREG_PCR: case MISCREG_PCR:
case MISCREG_PIC: case MISCREG_PIC:
panic("ASR number %d not implemented\n", miscReg - AsrStart); panic("ASR number %d not implemented\n", miscReg - AsrStart);
case MISCREG_GSR: case MISCREG_GSR:
gsr = val; gsr = val;
break;
case MISCREG_SOFTINT: case MISCREG_SOFTINT:
softint = val; softint = val;
return NoFault; break;
case MISCREG_TICK_CMPR: case MISCREG_TICK_CMPR:
tick_cmpr = val; tick_cmpr = val;
return NoFault; break;
case MISCREG_STICK: case MISCREG_STICK:
stick = val; stick = val;
return NoFault; break;
case MISCREG_STICK_CMPR: case MISCREG_STICK_CMPR:
stick_cmpr = val; stick_cmpr = val;
return NoFault; break;
/** Privilged Registers */ /** Privilged Registers */
case MISCREG_TPC: case MISCREG_TPC:
tpc[tl-1] = val; tpc[tl-1] = val;
return NoFault; break;
case MISCREG_TNPC: case MISCREG_TNPC:
tnpc[tl-1] = val; tnpc[tl-1] = val;
return NoFault; break;
case MISCREG_TSTATE: case MISCREG_TSTATE:
tstate[tl-1] = val; tstate[tl-1] = val;
return NoFault; break;
case MISCREG_TT: case MISCREG_TT:
tt[tl-1] = val; tt[tl-1] = val;
return NoFault; break;
case MISCREG_PRIVTICK: case MISCREG_PRIVTICK:
panic("Priviliged access to tick regesiters not implemented\n"); panic("Priviliged access to tick regesiters not implemented\n");
case MISCREG_TBA: case MISCREG_TBA:
tba = val; // clear lower 7 bits on writes.
return NoFault; tba = val & ULL(~0x7FFF);
break;
case MISCREG_PSTATE: case MISCREG_PSTATE:
pstate = val; pstate = val;
return NoFault; break;
case MISCREG_TL: case MISCREG_TL:
tl = val; tl = val;
return NoFault; break;
case MISCREG_PIL: case MISCREG_PIL:
pil = val; pil = val;
return NoFault; break;
case MISCREG_CWP: case MISCREG_CWP:
cwp = val; cwp = val;
return NoFault; break;
case MISCREG_CANSAVE: case MISCREG_CANSAVE:
cansave = val; cansave = val;
return NoFault; break;
case MISCREG_CANRESTORE: case MISCREG_CANRESTORE:
canrestore = val; canrestore = val;
return NoFault; break;
case MISCREG_CLEANWIN: case MISCREG_CLEANWIN:
cleanwin = val; cleanwin = val;
return NoFault; break;
case MISCREG_OTHERWIN: case MISCREG_OTHERWIN:
otherwin = val; otherwin = val;
return NoFault; break;
case MISCREG_WSTATE: case MISCREG_WSTATE:
wstate = val; wstate = val;
return NoFault; break;
case MISCREG_GL: case MISCREG_GL:
gl = val; gl = val;
return NoFault; break;
/** Hyper privileged registers */ /** Hyper privileged registers */
case MISCREG_HPSTATE: case MISCREG_HPSTATE:
hpstate = val; hpstate = val;
return NoFault; break;
case MISCREG_HTSTATE: case MISCREG_HTSTATE:
htstate[tl-1] = val; htstate[tl-1] = val;
return NoFault; break;
case MISCREG_HINTP: case MISCREG_HINTP:
panic("HINTP not implemented\n"); panic("HINTP not implemented\n");
case MISCREG_HTBA: case MISCREG_HTBA:
htba = val; htba = val;
return NoFault; break;
case MISCREG_STRAND_STS_REG: case MISCREG_STRAND_STS_REG:
strandStatusReg = val; strandStatusReg = val;
return NoFault; break;
case MISCREG_HSTICK_CMPR: case MISCREG_HSTICK_CMPR:
hstick_cmpr = val; hstick_cmpr = val;
return NoFault; break;
/** Floating Point Status Register */ /** Floating Point Status Register */
case MISCREG_FSR: case MISCREG_FSR:
fsr = val; fsr = val;
return NoFault; break;
default: default:
panic("Miscellaneous register %d not implemented\n", miscReg); panic("Miscellaneous register %d not implemented\n", miscReg);
} }
} }
Fault MiscRegFile::setRegWithEffect(int miscReg, void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc) const MiscReg &val, ThreadContext * tc)
{ {
const uint64_t Bit64 = (1ULL << 63); const uint64_t Bit64 = (1ULL << 63);
switch (miscReg) { switch (miscReg) {
case MISCREG_Y:
case MISCREG_CCR:
case MISCREG_ASI:
setReg(miscReg, val);
return NoFault;
case MISCREG_PRIVTICK:
case MISCREG_TICK: case MISCREG_TICK:
if (isNonPriv())
return new PrivilegedOpcode;
if (isPriv())
return new PrivilegedAction;
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64; tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
tickFields.npt = val & Bit64 ? 1 : 0; tickFields.npt = val & Bit64 ? 1 : 0;
return NoFault; break;
case MISCREG_PC:
return new IllegalInstruction;
case MISCREG_FPRS: case MISCREG_FPRS:
return new UnimpFault("FPU not implemented\n"); //Configure the fpu based on the fprs
break;
case MISCREG_PCR: case MISCREG_PCR:
return new UnimpFault("Performance Instrumentation not impl\n"); //Set up performance counting based on pcr value
case MISCREG_PIC: break;
return new UnimpFault("Performance Instrumentation not impl\n");
case MISCREG_GSR:
return setReg(miscReg, val);
/** Privilged Registers */
case MISCREG_TPC:
case MISCREG_TNPC:
case MISCREG_TSTATE:
case MISCREG_TT:
if (tl == 0)
return new IllegalInstruction;
setReg(miscReg, val);
return NoFault;
case MISCREG_TBA:
// clear lower 7 bits on writes.
setReg(miscReg, val & ULL(~0x7FFF));
return NoFault;
case MISCREG_PSTATE:
setReg(miscReg, val);
return NoFault;
case MISCREG_TL:
if (isHyperPriv() && val > MaxTL)
setReg(miscReg, MaxTL);
else if (isPriv() && !isHyperPriv() && val > MaxPTL)
setReg(miscReg, MaxPTL);
else
setReg(miscReg, val);
return NoFault;
case MISCREG_CWP: case MISCREG_CWP:
tc->changeRegFileContext(CONTEXT_CWP, val); tc->changeRegFileContext(CONTEXT_CWP, val);
case MISCREG_CANSAVE: break;
case MISCREG_CANRESTORE:
case MISCREG_CLEANWIN:
case MISCREG_OTHERWIN:
case MISCREG_WSTATE:
setReg(miscReg, val);
return NoFault;
case MISCREG_GL: case MISCREG_GL:
int newval; tc->changeRegFileContext(CONTEXT_GLOBALS, val);
if (isHyperPriv() && val > MaxGL) break;
newval = MaxGL;
else if (isPriv() && !isHyperPriv() && val > MaxPGL)
newval = MaxPGL;
else
newval = val;
tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
setReg(miscReg, newval);
return NoFault;
/** Floating Point Status Register */
case MISCREG_FSR:
panic("Floating Point not implemented\n");
default:
#if FULL_SYSTEM
setFSRegWithEffect(miscReg, val, tc);
#else
return new IllegalInstruction;
#endif
} }
setReg(miscReg, val);
} }
void MiscRegFile::serialize(std::ostream & os) void MiscRegFile::serialize(std::ostream & os)

25
src/arch/sparc/miscregfile.hh
View file

@ -56,7 +56,6 @@ namespace SparcISA
MISCREG_CCR = AsrStart + 2, MISCREG_CCR = AsrStart + 2,
MISCREG_ASI = AsrStart + 3, MISCREG_ASI = AsrStart + 3,
MISCREG_TICK = AsrStart + 4, MISCREG_TICK = AsrStart + 4,
MISCREG_PC = AsrStart + 5,
MISCREG_FPRS = AsrStart + 6, MISCREG_FPRS = AsrStart + 6,
MISCREG_PCR = AsrStart + 16, MISCREG_PCR = AsrStart + 16,
MISCREG_PIC = AsrStart + 17, MISCREG_PIC = AsrStart + 17,
@ -366,31 +365,13 @@ namespace SparcISA
reset(); reset();
} }
/** read a value out of an either an SE or FS IPR. No checking is done
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
* register are copied that are necessary for FS. However this prevents
* a bunch of ifdefs and is rarely called so is not performance
* criticial. */
MiscReg readReg(int miscReg); MiscReg readReg(int miscReg);
/** Read a value from an IPR. Only the SE iprs are here and the rest MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
* Checking is done for permission based on state bits in the miscreg
* file. */
MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
/** write a value into an either an SE or FS IPR. No checking is done void setReg(int miscReg, const MiscReg &val);
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
* register are copied that are necessary for FS. However this prevents
* a bunch of ifdefs and is rarely called so is not performance
* criticial.*/
Fault setReg(int miscReg, const MiscReg &val);
/** Write a value into an IPR. Only the SE iprs are here and the rest void setRegWithEffect(int miscReg,
* are are setFSRegWithEffect (which is called by setRegWithEffect()).
* Checking is done for permission based on state bits in the miscreg
* file. */
Fault setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc); const MiscReg &val, ThreadContext * tc);
void serialize(std::ostream & os); void serialize(std::ostream & os);

106
src/arch/sparc/process.cc
View file

@ -66,6 +66,10 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
// Set pointer for next thread stack. Reserve 8M for main stack. // Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024); next_thread_stack_base = stack_base - (8 * 1024 * 1024);
//Initialize these to 0s
fillStart = 0;
spillStart = 0;
} }
void void
@ -88,15 +92,19 @@ SparcLiveProcess::startup()
*/ */
//No windows contain info from other programs //No windows contain info from other programs
threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
//There are no windows to pop //There are no windows to pop
threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
//All windows are available to save into //All windows are available to save into
threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
//All windows are "clean" //All windows are "clean"
threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
//Start with register window 0 //Start with register window 0
threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
//Always use spill and fill traps 0
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
//Set the trap level to 0
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
} }
m5_auxv_t buildAuxVect(int64_t type, int64_t val) m5_auxv_t buildAuxVect(int64_t type, int64_t val)
@ -107,6 +115,83 @@ m5_auxv_t buildAuxVect(int64_t type, int64_t val)
return result; return result;
} }
//We only use 19 instructions for the trap handlers, but there would be
//space for 32 in a real SPARC trap table.
const int numFillInsts = 32;
const int numSpillInsts = 32;
MachInst fillHandler[numFillInsts] =
{
htog(0x87802018), //wr %g0, ASI_AIUP, %asi
htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0
htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1
htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2
htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3
htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4
htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5
htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6
htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7
htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0
htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1
htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2
htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3
htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4
htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5
htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6
htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7
htog(0x83880000), //restored
htog(0x83F00000), //retry
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000) //illtrap
};
MachInst spillHandler[numSpillInsts] =
{
htog(0x87802018), //wr %g0, ASI_AIUP, %asi
htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi
htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi
htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi
htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi
htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi
htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi
htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi
htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi
htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi
htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi
htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi
htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi
htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi
htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi
htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi
htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi
htog(0x81880000), //saved
htog(0x83F00000), //retry
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000), //illtrap
htog(0x00000000) //illtrap
};
void void
SparcLiveProcess::argsInit(int intSize, int pageSize) SparcLiveProcess::argsInit(int intSize, int pageSize)
{ {
@ -317,6 +402,17 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
//Stuff the trap handlers into the processes address space.
//Since the stack grows down and is the highest area in the processes
//address space, we can put stuff above it and stay out of the way.
int fillSize = sizeof(MachInst) * numFillInsts;
int spillSize = sizeof(MachInst) * numSpillInsts;
fillStart = stack_base;
spillStart = fillStart + fillSize;
initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize);
initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize);
//Set up the thread context to start running the process
threadContexts[0]->setIntReg(ArgumentReg0, argc); threadContexts[0]->setIntReg(ArgumentReg0, argc);
threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);

9
src/arch/sparc/process.hh
View file

@ -55,6 +55,9 @@ class SparcLiveProcess : public LiveProcess
static const Addr StackBias = 2047; static const Addr StackBias = 2047;
//The locations of the fill and spill handlers
Addr fillStart, spillStart;
std::vector<m5_auxv_t> auxv; std::vector<m5_auxv_t> auxv;
SparcLiveProcess(const std::string &nm, ObjectFile *objFile, SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
@ -71,6 +74,12 @@ class SparcLiveProcess : public LiveProcess
void argsInit(int intSize, int pageSize); void argsInit(int intSize, int pageSize);
Addr readFillStart()
{ return fillStart; }
Addr readSpillStart()
{ return spillStart; }
}; };
#endif // __SPARC_PROCESS_HH__ #endif // __SPARC_PROCESS_HH__

9
src/arch/sparc/regfile.cc
View file

@ -82,18 +82,21 @@ MiscReg RegFile::readMiscReg(int miscReg)
MiscReg RegFile::readMiscRegWithEffect(int miscReg, MiscReg RegFile::readMiscRegWithEffect(int miscReg,
Fault &fault, ThreadContext *tc) Fault &fault, ThreadContext *tc)
{ {
return miscRegFile.readRegWithEffect(miscReg, fault, tc); fault = NoFault;
return miscRegFile.readRegWithEffect(miscReg, tc);
} }
Fault RegFile::setMiscReg(int miscReg, const MiscReg &val) Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
{ {
return miscRegFile.setReg(miscReg, val); miscRegFile.setReg(miscReg, val);
return NoFault;
} }
Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val, Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
ThreadContext * tc) ThreadContext * tc)
{ {
return miscRegFile.setRegWithEffect(miscReg, val, tc); miscRegFile.setRegWithEffect(miscReg, val, tc);
return NoFault;
} }
FloatReg RegFile::readFloatReg(int floatReg, int width) FloatReg RegFile::readFloatReg(int floatReg, int width)

24
src/base/bitfield.hh
View file

@ -69,4 +69,28 @@ sext(uint64_t val)
return sign_bit ? (val | ~mask(N)) : val; return sign_bit ? (val | ~mask(N)) : val;
} }
/**
* Return val with bits first to last set to bit_val
*/
template <class T, class B>
inline
T
insertBits(T val, int first, int last, B bit_val)
{
T bmask = mask(first - last + 1) << last;
return ((bit_val << last) & bmask) | (val & ~bmask);
}
/**
* A convenience function to replace bits first to last of val with bit_val
* in place.
*/
template <class T, class B>
inline
void
replaceBits(T& val, int first, int last, B bit_val)
{
val = insertBits(val, first, last, bit_val);
}
#endif // __BASE_BITFIELD_HH__ #endif // __BASE_BITFIELD_HH__

2
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
View file

@ -91,6 +91,8 @@ uid=100
[system.membus] [system.membus]
type=Bus type=Bus
bus_id=0 bus_id=0
clock=1000
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem] [system.physmem]

2
tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out
View file

@ -19,6 +19,8 @@ mem_mode=atomic
[system.membus] [system.membus]
type=Bus type=Bus
bus_id=0 bus_id=0
clock=1000
width=64
[system.cpu.workload] [system.cpu.workload]
type=LiveProcess type=LiveProcess

18
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
View file

@ -1,18 +1,18 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 2175 # Simulator instruction rate (inst/s) host_inst_rate 58121 # Simulator instruction rate (inst/s)
host_mem_usage 147292 # Number of bytes of host memory used host_mem_usage 148396 # Number of bytes of host memory used
host_seconds 2.06 # Real time elapsed on the host host_seconds 0.08 # Real time elapsed on the host
host_tick_rate 2174 # Simulator tick rate (ticks/s) host_tick_rate 57840 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4483 # Number of instructions simulated sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated sim_seconds 0.000000 # Number of seconds simulated
sim_ticks 4482 # Number of ticks simulated sim_ticks 4862 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 4483 # number of cpu cycles simulated system.cpu.numCycles 4863 # number of cpu cycles simulated
system.cpu.num_insts 4483 # Number of instructions executed system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 965 # Number of memory references system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
View file

@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 8 2006 14:19:59 M5 compiled Oct 27 2006 02:07:29
M5 started Sun Oct 8 14:20:03 2006 M5 started Fri Oct 27 02:08:08 2006
M5 executing on zizzer.eecs.umich.edu M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Exiting @ tick 4482 because target called exit() Exiting @ tick 4862 because target called exit()

1
tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
View file

@ -20,7 +20,6 @@ print_effaddr=true
print_fetchseq=false print_fetchseq=false
print_iregs=false print_iregs=false
print_opclass=true print_opclass=true
print_reg_delta=false
print_thread=true print_thread=true
speculative=true speculative=true
trace_system=client trace_system=client

232
tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt
View file

@ -1,67 +1,67 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
host_inst_rate 53689 # Simulator instruction rate (inst/s) host_inst_rate 48159 # Simulator instruction rate (inst/s)
host_mem_usage 177104 # Number of bytes of host memory used host_mem_usage 179620 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 17808084 # Simulator tick rate (ticks/s) host_tick_rate 15510230 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4483 # Number of instructions simulated sim_insts 4863 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated sim_seconds 0.000002 # Number of seconds simulated
sim_ticks 1497001 # Number of ticks simulated sim_ticks 1573001 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 464 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 3972.166667 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2972.166667 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 410 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency 214497 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.116379 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency 160497 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.116379 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 501 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 3980.840580 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2980.840580 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 432 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency 274678 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.137725 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 69 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency 205678 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.137725 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 69 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.845528 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 8.195652 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 965 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 3977.032520 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
system.cpu.dcache.demand_hits 842 # number of demand (read+write) hits system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 489175 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.127461 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses
system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 366175 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.127461 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 123 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 965 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 3977.032520 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2977.032520 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 842 # number of overall hits system.cpu.dcache.overall_hits 1131 # number of overall hits
system.cpu.dcache.overall_miss_latency 489175 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.127461 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses
system.cpu.dcache.overall_misses 123 # number of overall misses system.cpu.dcache.overall_misses 138 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 366175 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.127461 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 123 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -74,56 +74,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 123 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse 71.370810 # Cycle average of tags in use system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use
system.cpu.dcache.total_refs 842 # Total number of references to valid blocks. system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 4484 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 3979.178571 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.178571 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 4232 # number of ReadReq hits system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency 1002753 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.056200 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 252 # number of ReadReq misses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency 750753 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.056200 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 252 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 16.793651 # Average number of references to valid blocks. system.cpu.icache.avg_refs 18 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 4484 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 3979.178571 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
system.cpu.icache.demand_hits 4232 # number of demand (read+write) hits system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency 1002753 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.056200 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses
system.cpu.icache.demand_misses 252 # number of demand (read+write) misses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 750753 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.056200 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 252 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 4484 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 3979.178571 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 2979.178571 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 4232 # number of overall hits system.cpu.icache.overall_hits 4608 # number of overall hits
system.cpu.icache.overall_miss_latency 1002753 # number of overall miss cycles system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.056200 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses
system.cpu.icache.overall_misses 252 # number of overall misses system.cpu.icache.overall_misses 256 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 750753 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.056200 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 252 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -136,57 +136,57 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 252 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse 115.914677 # Cycle average of tags in use system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use
system.cpu.icache.total_refs 4232 # Total number of references to valid blocks. system.cpu.icache.total_refs 4608 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 375 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 394 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 2986.473118 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1985.473118 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 1110968 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.992000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.992386 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 372 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 738596 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992386 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 372 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0.008065 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.007673 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 375 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 394 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 2986.473118 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency 1110968 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992000 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.992386 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 372 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 738596 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992000 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.992386 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 372 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 375 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 394 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 2986.473118 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1985.473118 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 3 # number of overall hits system.cpu.l2cache.overall_hits 3 # number of overall hits
system.cpu.l2cache.overall_miss_latency 1110968 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.992386 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 372 # number of overall misses system.cpu.l2cache.overall_misses 391 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 738596 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.992386 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 372 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
@ -199,16 +199,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 372 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse 185.896040 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1497001 # number of cpu cycles simulated system.cpu.numCycles 1573001 # number of cpu cycles simulated
system.cpu.num_insts 4483 # Number of instructions executed system.cpu.num_insts 4863 # Number of instructions executed
system.cpu.num_refs 965 # Number of memory references system.cpu.num_refs 1269 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

8
tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout
View file

@ -5,8 +5,8 @@ The Regents of The University of Michigan
All Rights Reserved All Rights Reserved
M5 compiled Oct 23 2006 07:47:36 M5 compiled Oct 27 2006 02:07:29
M5 started Mon Oct 23 07:47:41 2006 M5 started Fri Oct 27 02:08:11 2006
M5 executing on zeep M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
Exiting @ tick 1497001 because target called exit() Exiting @ tick 1573001 because target called exit()