From f9346d25c8e2148a2eea06d8ce7126cc2b487527 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 17 Aug 2009 18:23:04 -0700
Subject: [PATCH] X86: Implement PXOR.

---
 src/arch/x86/isa/decoder/two_byte_opcodes.isa |  4 ++--
 .../simd128/integer/logical/exclusive_or.py   | 22 ++++++++++++++++++-
 .../simd64/integer/logical/exclusive_or.py    | 15 ++++++++++++-
 3 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 5bfe69dc5..8c49f02f5 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -1050,7 +1050,7 @@
                     0x4: paddsb_Pq_Qq();
                     0x5: paddsw_Pq_Qq();
                     0x6: pmaxsw_Pq_Qq();
-                    0x7: pxor_Pq_Qq();
+                    0x7: Inst::PXOR(Pq,Qq);
                 }
                 // operand size (0x66)
                 0x1: decode OPCODE_OP_BOTTOM3 {
@@ -1061,7 +1061,7 @@
                     0x4: paddsb_Vo_Wo();
                     0x5: paddsw_Vo_Wo();
                     0x6: pmaxsw_Vo_Wo();
-                    0x7: pxor_Vo_Wo();
+                    0x7: Inst::PXOR(Vo,Wo);
                 }
                 default: Inst::UD2();
             }
diff --git a/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py b/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py
index 336796e23..e72deae0d 100644
--- a/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py
+++ b/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py
@@ -54,5 +54,25 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PXOR
+def macroop PXOR_XMM_XMM {
+    mxor xmml, xmml, xmmlm
+    mxor xmmh, xmmh, xmmhm
+};
+
+def macroop PXOR_XMM_M {
+    lea t1, seg, sib, disp, dataSize=asz
+    ldfp ufp1, seg, [1, t0, t1], dataSize=8
+    ldfp ufp2, seg, [1, t0, t1], 8, dataSize=8
+    mxor xmml, xmml, ufp1
+    mxor xmmh, xmmh, ufp2
+};
+
+def macroop PXOR_XMM_P {
+    rdip t7
+    lea t1, seg, riprel, disp, dataSize=asz
+    ldfp ufp1, seg, [1, t0, t1], dataSize=8
+    ldfp ufp2, seg, [1, t0, t1], 8, dataSize=8
+    mxor xmml, xmml, ufp1
+    mxor xmmh, xmmh, ufp2
+};
 '''
diff --git a/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py b/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py
index 336796e23..3e70093e0 100644
--- a/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py
+++ b/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py
@@ -54,5 +54,18 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PXOR
+def macroop PXOR_MMX_MMX {
+    mxor mmx, mmx, mmxm
+};
+
+def macroop PXOR_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    mxor mmx, mmx, ufp1
+};
+
+def macroop PXOR_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    mxor mmx, mmx, ufp1
+};
 '''