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Merge zizzer:/bk/newmem

Browse source 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : a4f80ce975a23ba9858e6bf2dbbfed8897dd1810
This commit is contained in:
Ali Saidi 2007-02-24 22:10:06 -05:00
commit f892608ff7
5 changed files with 24 additions and 34 deletions
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5
src/arch/sparc/isa/decoder.isa
View file

@ -1015,6 +1015,11 @@ decode OP default Unknown::unknown()
// we have 7 bits of space here to play with... // we have 7 bits of space here to play with...
0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
}}, No_OpClass, IsNonSpeculative); }}, No_OpClass, IsNonSpeculative);
0x50: m5readfile({{
O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
}}, IsNonSpeculative);
0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x54: m5panic({{ 0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC()); panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, No_OpClass, IsNonSpeculative); }}, No_OpClass, IsNonSpeculative);

12
src/arch/sparc/isa/operands.isa
View file

@ -100,12 +100,12 @@ def operands {{
'R1': ('IntReg', 'udw', '1', None, 7), 'R1': ('IntReg', 'udw', '1', None, 7),
'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
'R16': ('IntReg', 'udw', '16', None, 9), 'R16': ('IntReg', 'udw', '16', None, 9),
'O0': ('IntReg', 'udw', '24', 'IsInteger', 10), 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
'O1': ('IntReg', 'udw', '25', 'IsInteger', 11), 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
'O2': ('IntReg', 'udw', '26', 'IsInteger', 12), 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
'O3': ('IntReg', 'udw', '27', 'IsInteger', 13), 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13),
'O4': ('IntReg', 'udw', '28', 'IsInteger', 14), 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14),
'O5': ('IntReg', 'udw', '29', 'IsInteger', 15), 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),
# Control registers # Control registers
# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), # 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),

4
util/m5/Makefile.sparc
View file

@ -35,7 +35,7 @@ CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld LD=$(CROSS_COMPILE)ld
CFLAGS=-O2 CFLAGS=-O2 -m64
OBJS=m5.o m5op_sparc.o OBJS=m5.o m5op_sparc.o
all: m5 all: m5
@ -47,7 +47,7 @@ all: m5
$(CC) $(CFLAGS) -o $@ -c $< $(CC) $(CFLAGS) -o $@ -c $<
m5: $(OBJS) m5: $(OBJS)
$(CC) -o $@ $(OBJS) $(CC) -m64 -o $@ $(OBJS)
clean: clean:
rm -f *.o m5 rm -f *.o m5

16
util/m5/m5.c
View file

@ -186,21 +186,5 @@ main(int argc, char *argv[])
m5_loadsymbol(arg1); m5_loadsymbol(arg1);
return 0; return 0;
} }
if (COMPARE("readfile")) {
char buf[256*1024];
int offset = 0;
int len;
if (argc != 2)
usage();
while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
write(STDOUT_FILENO, buf, len);
offset += len;
}
return 0;
}
usage(); usage();
} }

21
util/m5/m5op_sparc.S
View file

@ -49,8 +49,10 @@ func:
#define END(func) \ #define END(func) \
.size func, (.-func) .size func, (.-func)
#define DEBUGBREAK INST(debugbreak_func, 0, 0, 0)
#define M5EXIT INST(exit_func, 0, 0, 0) #define M5EXIT INST(exit_func, 0, 0, 0)
#define PANIC INST(panic_func, 0, 0, 0) #define PANIC INST(panic_func, 0, 0, 0)
#define READFILE INST(readfile_func, 0, 0, 0)
LEAF(m5_exit) LEAF(m5_exit)
retl retl
@ -62,6 +64,15 @@ LEAF(m5_panic)
PANIC PANIC
END(m5_panic) END(m5_panic)
LEAF(m5_readfile)
retl
READFILE
END(m5_readfile)
LEAF(m5_debugbreak)
retl
DEBUGBREAK
END(m5_debugbreak)
/* !!!!!! All code below here just panics !!!!!! */ /* !!!!!! All code below here just panics !!!!!! */
LEAF(arm) LEAF(arm)
@ -119,16 +130,6 @@ LEAF(m5_checkpoint)
PANIC PANIC
END(m5_checkpoint) END(m5_checkpoint)
LEAF(m5_readfile)
retl
PANIC
END(m5_readfile)
LEAF(m5_debugbreak)
retl
PANIC
END(m5_debugbreak)
LEAF(m5_switchcpu) LEAF(m5_switchcpu)
retl retl
PANIC PANIC