mem: Align cache behaviour in atomic when upstream is responding
Adopt the same flow as in timing mode, where the caches on the path to memory get to keep the line (if present), and we use the responderHadWritable flag to determine if we need to forward the (invalidating) packet or not.
This commit is contained in:
parent
986214f181
commit
f84ee031cc
36
src/mem/cache/cache.cc
vendored
36
src/mem/cache/cache.cc
vendored
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@ -1011,8 +1011,6 @@ Cache::recvAtomic(PacketPtr pkt)
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{
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{
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// We are in atomic mode so we pay just for lookupLatency here.
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// We are in atomic mode so we pay just for lookupLatency here.
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Cycles lat = lookupLatency;
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Cycles lat = lookupLatency;
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// @TODO: make this a parameter
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bool last_level_cache = false;
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// Forward the request if the system is in cache bypass mode.
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// Forward the request if the system is in cache bypass mode.
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if (system->bypassCaches())
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if (system->bypassCaches())
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@ -1020,30 +1018,18 @@ Cache::recvAtomic(PacketPtr pkt)
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promoteWholeLineWrites(pkt);
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promoteWholeLineWrites(pkt);
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// follow the same flow as in recvTimingReq, and check if a cache
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// above us is responding
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if (pkt->cacheResponding()) {
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if (pkt->cacheResponding()) {
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// have to invalidate ourselves and any lower caches even if
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DPRINTF(Cache, "Cache above responding to %#llx (%s): "
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// upper cache will be responding
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"not responding\n",
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if (pkt->isInvalidate()) {
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pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
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CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
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if (blk && blk->isValid()) {
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// if a cache is responding, and it had the line in Owned
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tags->invalidate(blk);
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// rather than Modified state, we need to invalidate any
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blk->invalidate();
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// copies that are not on the same path to memory
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DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
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if (pkt->needsWritable() && !pkt->responderHadWritable()) {
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" invalidating\n",
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lat += ticksToCycles(memSidePort->sendAtomic(pkt));
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pkt->cmdString(), pkt->getAddr(),
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pkt->isSecure() ? "s" : "ns");
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}
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if (!last_level_cache) {
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DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
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" forwarding\n",
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pkt->cmdString(), pkt->getAddr(),
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pkt->isSecure() ? "s" : "ns");
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lat += ticksToCycles(memSidePort->sendAtomic(pkt));
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}
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} else {
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DPRINTF(Cache, "Other cache responding to %s on %#llx: "
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"not responding\n",
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pkt->cmdString(), pkt->getAddr());
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}
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}
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return lat * clockPeriod();
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return lat * clockPeriod();
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