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Implemented and hooked in xchg, rotate with carry, and ret instructions

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--HG--
extra : convert_revision : a8e67b0ab4072308f01e0df7f7ee05b31f605a35
This commit is contained in:
Gabe Black 2007-07-21 19:29:39 -07:00
parent ee6fbdc28b
commit f7ff068b30
5 changed files with 204 additions and 58 deletions
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109
src/arch/x86/isa/decoder/one_byte_opcodes.isa
View file

@ -232,8 +232,8 @@
0x7: JNLE(Jb);
}
}
0x10: decode OPCODE_OP_BOTTOM3 {
format Inst {
format Inst {
0x10: decode OPCODE_OP_BOTTOM3 {
//0x0: group1_Eb_Ib();
0x0: decode MODRM_REG {
0x0: ADD(Eb,Ib);
@ -281,11 +281,11 @@
0x6: XOR(Ev,Ib);
0x7: CMP(Ev,Ib);
}
0x4: Inst::TEST(Eb,Gb);
0x5: Inst::TEST(Ev,Gv);
0x4: TEST(Eb,Gb);
0x5: TEST(Ev,Gv);
0x6: XCHG(Eb,Gb);
0x7: XCHG(Ev,Gv);
}
0x6: xchg_Eb_Gb();
0x7: xchg_Ev_Gv();
}
0x11: decode OPCODE_OP_BOTTOM3 {
0x0: Inst::MOV(Eb,Gb);
@ -342,57 +342,52 @@
0x6: scas_Yb_Al();
0x7: scas_Yv_rAX();
}
0x16: decode OPCODE_OP_BOTTOM3 {
0x0: mov_Al_Ib();
0x1: mov_Cl_Ib();
0x2: mov_Dl_Ib();
0x3: mov_Bl_Ib();
0x4: mov_Ah_Ib();
0x5: mov_Ch_Ib();
0x6: mov_Dh_Ib();
0x7: mov_Bh_Ib();
}
0x17: Inst::MOV(B,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_Ib();
0x0: decode MODRM_REG {
0x0: Inst::ROL(Eb,Ib);
0x1: Inst::ROR(Eb,Ib);
0x2: rcl_Eb_Ib();
0x3: rcr_Eb_Ib();
0x4: Inst::SAL(Eb,Ib);
0x5: Inst::SHR(Eb,Ib);
0x6: Inst::SAL(Eb,Ib);
0x7: Inst::SAR(Eb,Ib);
}
//0x1: group2_Ev_Ib();
0x1: decode MODRM_REG {
0x0: Inst::ROL(Ev,Ib);
0x1: Inst::ROR(Ev,Ib);
0x2: rcl_Ev_Ib();
0x3: rcr_Ev_Ib();
0x4: Inst::SAL(Ev,Ib);
0x5: Inst::SHR(Ev,Ib);
0x6: Inst::SAL(Ev,Ib);
0x7: Inst::SAR(Ev,Ib);
}
0x2: ret_near_Iw();
0x3: Inst::RET_NEAR();
0x4: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: les_Gz_Mp();
}
0x5: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: lds_Gz_Mp();
}
//0x6: group12_Eb_Ib();
0x6: decode MODRM_REG {
0x0: Inst::MOV(Eb,Ib);
}
//0x7: group12_Ev_Iz();
0x7: decode MODRM_REG {
0x0: Inst::MOV(Ev,Iz);
format Inst {
0x16: MOV(B,Ib);
0x17: MOV(B,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_Ib();
0x0: decode MODRM_REG {
0x0: ROL(Eb,Ib);
0x1: ROR(Eb,Ib);
0x2: RCL(Eb,Ib);
0x3: RCR(Eb,Ib);
0x4: SAL(Eb,Ib);
0x5: SHR(Eb,Ib);
0x6: SAL(Eb,Ib);
0x7: SAR(Eb,Ib);
}
//0x1: group2_Ev_Ib();
0x1: decode MODRM_REG {
0x0: ROL(Ev,Ib);
0x1: ROR(Ev,Ib);
0x2: RCL(Ev,Ib);
0x3: RCR(Ev,Ib);
0x4: SAL(Ev,Ib);
0x5: SHR(Ev,Ib);
0x6: SAL(Ev,Ib);
0x7: SAR(Ev,Ib);
}
0x2: RET_NEAR(Iw);
0x3: RET_NEAR();
0x4: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::les_Gz_Mp();
}
0x5: decode MODE_SUBMODE {
0x0: UD2();
default: WarnUnimpl::lds_Gz_Mp();
}
//0x6: group12_Eb_Ib();
0x6: decode MODRM_REG {
0x0: MOV(Eb,Ib);
default: UD2();
}
//0x7: group12_Ev_Iz();
0x7: decode MODRM_REG {
0x0: MOV(Ev,Iz);
default: UD2();
}
}
}
0x19: decode OPCODE_OP_BOTTOM3 {

12
src/arch/x86/isa/insts/control_transfer/xreturn.py
View file

@ -63,4 +63,16 @@ def macroop RET_NEAR
addi rsp, rsp, dsz
wripi t1, 0
};
def macroop RET_NEAR_I
{
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm t2, imm
ld t1, ss, [0, t0, rsp]
addi rsp, rsp, dsz
add rsp, rsp, t2
wripi t1, 0
};
'''

3
src/arch/x86/isa/insts/data_transfer/__init__.py
View file

@ -55,7 +55,8 @@
categories = ["conditional_move",
"move",
"stack_operations"]
"stack_operations",
"xchg"]
microcode = ""
for category in categories:

98
src/arch/x86/isa/insts/data_transfer/xchg.py Normal file
View file

@ -0,0 +1,98 @@
# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
# compensation for, or commercial advantage from such use. Illustrative
# examples of non-commercial use are academic research, personal study,
# teaching, education and corporate research & development.
# Illustrative examples of commercial use are distributing products for
# commercial advantage and providing services using the software for
# commercial advantage.
#
# If you wish to use this software or functionality therein that may be
# covered by patents for commercial use, please contact:
# Director of Intellectual Property Licensing
# Office of Strategy and Technology
# Hewlett-Packard Company
# 1501 Page Mill Road
# Palo Alto, California 94304
#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer. Redistributions
# in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution. Neither the name of
# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission. No right of
# sublicense is granted herewith. Derivatives of the software and
# output created using the software may be prepared, but only for
# Non-Commercial Uses. Derivatives of the software may be shared with
# others provided: (i) the others agree to abide by the list of
# conditions herein which includes the Non-Commercial Use restrictions;
# and (ii) such Derivatives of the software include the above copyright
# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
# All the memory versions need to use LOCK, regardless of if it was set
def macroop XCHG_R_R
{
# Use the xor trick instead of moves to reduce register pressure.
# This probably doesn't make much of a difference, but it's easy.
xor reg, reg, regm
xor regm, regm, reg
xor reg, reg, regm
};
def macroop XCHG_R_M
{
ld t1, ds, [scale, index, base], disp
st reg, ds, [scale, index, base], disp
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
st reg, ds, [0, t0, t7], disp
mov reg, reg, t1
};
def macroop XCHG_M_R
{
ld t1, ds, [scale, index, base], disp
st reg, ds, [scale, index, base], disp
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
st reg, ds, [0, t0, t7], disp
mov reg, reg, t1
};
'''

40
src/arch/x86/isa/insts/rotate_and_shift/rotate.py
View file

@ -93,6 +93,46 @@ def macroop ROR_P_I
ror t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop RCL_R_I
{
rcl reg, reg, imm
};
def macroop RCL_M_I
{
ld t1, ds, [scale, index, base], disp
rcl t1, t1, imm
st t1, ds, [scale, index, base], disp
};
def macroop RCL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcl t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop RCR_R_I
{
rcr reg, reg, imm
};
def macroop RCR_M_I
{
ld t1, ds, [scale, index, base], disp
rcr t1, t1, imm
st t1, ds, [scale, index, base], disp
};
def macroop RCR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcr t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class RCL(Inst):