diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 9785e217c..93863b50d 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -1,5 +1,17 @@
 // -*- mode:c++ -*-
 
+// Copyright (c) 2013 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
 // Copyright (c) 2003-2006 The Regents of The University of Michigan
 // All rights reserved.
 //
@@ -929,7 +941,14 @@ decode OPCODE default Unknown::unknown() {
                 PseudoInst::arm(xc->tcBase());
             }}, IsNonSpeculative);
             0x01: quiesce({{
-                PseudoInst::quiesce(xc->tcBase());
+                // Don't sleep if (unmasked) interrupts are pending
+                Interrupts* interrupts =
+                    xc->tcBase()->getCpuPtr()->getInterruptController();
+                if (interrupts->checkInterrupts(xc->tcBase())) {
+                    PseudoInst::quiesceSkip(xc->tcBase());
+                } else {
+                    PseudoInst::quiesce(xc->tcBase());
+                }
             }}, IsNonSpeculative, IsQuiesce);
             0x02: quiesceNs({{
                 PseudoInst::quiesceNs(xc->tcBase(), R16);