SPARC: Make sure unaligned access are caught on cached translations as well.
--HG-- extra : convert_revision : 5c1f3f585817a19a771164f809dfc2fdc1ab3fb2
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1 changed files with 42 additions and 37 deletions
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@ -569,6 +569,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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asi = (ASI)req->getAsi();
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asi = (ASI)req->getAsi();
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bool implicit = false;
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bool implicit = false;
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bool hpriv = bits(tlbdata,0,0);
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bool hpriv = bits(tlbdata,0,0);
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bool unaligned = (vaddr & size-1);
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DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
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DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
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vaddr, size, asi);
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vaddr, size, asi);
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@ -579,6 +580,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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if (asi == ASI_IMPLICIT)
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if (asi == ASI_IMPLICIT)
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implicit = true;
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implicit = true;
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// Only use the fast path here if there doesn't need to be an unaligned
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// trap later
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if (!unaligned) {
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if (hpriv && implicit) {
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if (hpriv && implicit) {
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req->setPaddr(vaddr & PAddrImplMask);
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req->setPaddr(vaddr & PAddrImplMask);
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return NoFault;
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return NoFault;
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@ -616,6 +620,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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} // if matched
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} // if matched
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} // if cache entry valid
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} // if cache entry valid
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}
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}
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}
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bool red = bits(tlbdata,1,1);
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bool red = bits(tlbdata,1,1);
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bool priv = bits(tlbdata,2,2);
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bool priv = bits(tlbdata,2,2);
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@ -707,7 +712,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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}
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}
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// If the asi is unaligned trap
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// If the asi is unaligned trap
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if (vaddr & size-1) {
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if (unaligned) {
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writeSfsr(vaddr, false, ct, false, OtherFault, asi);
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writeSfsr(vaddr, false, ct, false, OtherFault, asi);
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return new MemAddressNotAligned;
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return new MemAddressNotAligned;
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}
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}
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