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ARM: Boot loader changes that make it more flexible about load and I/O addrs

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This commit is contained in:
Prakash Ramrakhyani 2011-05-04 20:38:27 -05:00
parent 307f089e7f
commit f738005266
2 changed files with 30 additions and 19 deletions
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18
system/arm/simple_bootloader/Makefile
View file

@ -34,25 +34,25 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# #
# Authors: Ali Saidi # Authors: Ali Saidi
# Prakash Ramrakhyani
# Need to have CROSS_COMPILE set to /path/to/bin/arm-none-eabi-
# arm-unknown-linux-gnu- might also work
#
#
CROSS_COMPILE=arm-none-eabi- # Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
# or have arm-unknown-linux-gnu in your path
CROSS_COMPILE?=arm-none-linux-gnueabi-
CC=$(CROSS_COMPILE)gcc CC=$(CROSS_COMPILE)gcc
CPP=$(CROSS_COMPILE)g++ CPP=$(CROSS_COMPILE)g++
LD=$(CROSS_COMPILE)ld LD=$(CROSS_COMPILE)ld
all: boot all: boot.arm
boot.o: boot.S boot.o: simple.S
$(CC) -mfloat-abi=softfp -march=armv7-a -mfpu=vfpv3 -mthumb -fno-builtin -nostdinc -o boot.o -c boot.S $(CC) -mfloat-abi=softfp -march=armv7-a -fno-builtin -nostdinc -o boot.o -c simple.S
boot.arm: boot.o boot.arm: boot.o
$(LD) -o boot.arm -N -Ttext 0 boot.o -non_shared -static $(LD) -o boot.arm -N -Ttext 0x80000000 boot.o -non_shared -static
clean: clean:

31
system/arm/simple_bootloader/simple.S
View file

@ -44,7 +44,7 @@
* *
* Upon executing this code: * Upon executing this code:
* r0 = 0, r1 = machine number, r2 = atags ptr * r0 = 0, r1 = machine number, r2 = atags ptr
* r3 = kernel start address * r3 = kernel start address, r4 = GIC address, r5 = flag register address
* *
* CPU 0 should branch to the kernel start address and it's done with * CPU 0 should branch to the kernel start address and it's done with
* the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends
@ -56,16 +56,27 @@
.extern main .extern main
_start: _start:
_entry: _entry:
mrc p15, 0, r4, c0, c0, 5 // get the MPIDR register b bootldr // All the interrupt vectors jump to the boot loader
uxtb r4, r4 // isolate the lower 8 bits (affinity lvl 1) b bootldr
adds r4, r4, #0 // set flags for branch b bootldr
b bootldr
b bootldr
b bootldr
b bootldr
b bootldr
b bootldr
bootldr:
mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
uxtb r8, r8 // isolate the lower 8 bits (affinity lvl 1)
adds r8, r8, #0 // set flags for branch
bxeq r3 // if it's 0 (CPU 0), branch to kernel bxeq r3 // if it's 0 (CPU 0), branch to kernel
mov r8, #1
str r8, [r4, #0] // Enable CPU interface on GIC
wfi // wait for an interrupt
pen: pen:
wfi // otherwise wait for an interrupt ldr r8, [r5] // load the value
mov r4, #0x30 // Build address of the system controller movs r8, r8 // set the flags on this value
movt r4, #0x1000 // flag register r4 = 0x10000030
ldr r5, [r4] // load the value
movs r5, r5 // set the flags on this value
beq pen // if it's zero try again beq pen // if it's zero try again
bx r5 // Jump to where we've been told bx r8 // Jump to where we've been told
bkpt // We should never get here bkpt // We should never get here