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stats: arm: updates

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This commit is contained in:
Nilay Vaish 2015-04-30 14:17:43 -05:00
parent 42fe2df354
commit f71fa17157
35 changed files with 10628 additions and 10624 deletions
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14
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.625396 # Nu
sim_ticks 2625395606000 # Number of ticks simulated sim_ticks 2625395606000 # Number of ticks simulated
final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 91005 # Simulator instruction rate (inst/s) host_inst_rate 72214 # Simulator instruction rate (inst/s)
host_op_rate 110413 # Simulator op (including micro ops) rate (op/s) host_op_rate 87615 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1985416078 # Simulator tick rate (ticks/s) host_tick_rate 1575454547 # Simulator tick rate (ticks/s)
host_mem_usage 586088 # Number of bytes of host memory used host_mem_usage 643232 # Number of bytes of host memory used
host_seconds 1322.34 # Real time elapsed on the host host_seconds 1666.44 # Real time elapsed on the host
sim_insts 120339436 # Number of instructions simulated sim_insts 120339436 # Number of instructions simulated
sim_ops 146004136 # Number of ops (including micro ops) simulated sim_ops 146004136 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
@ -779,9 +779,9 @@ system.cpu0.iew.iewDispNonSpecInsts 851019 # Nu
system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedTakenIncorrect 275682 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute system.cpu0.iew.branchMispredicts 650409 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute

760
tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.061589 # Number of seconds simulated sim_seconds 0.061594 # Number of seconds simulated
sim_ticks 61589191500 # Number of ticks simulated sim_ticks 61594138500 # Number of ticks simulated
final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169101 # Simulator instruction rate (inst/s) host_inst_rate 196979 # Simulator instruction rate (inst/s)
host_op_rate 169943 # Simulator op (including micro ops) rate (op/s) host_op_rate 197960 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 114949938 # Simulator tick rate (ticks/s) host_tick_rate 133911114 # Simulator tick rate (ticks/s)
host_mem_usage 374724 # Number of bytes of host memory used host_mem_usage 438496 # Number of bytes of host memory used
host_seconds 535.79 # Real time elapsed on the host host_seconds 459.96 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated sim_insts 90602850 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.readReqs 15574 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -47,7 +47,7 @@ system.physmem.perBankRdBursts::2 949 # Pe
system.physmem.perBankRdBursts::3 1028 # Per bank write bursts system.physmem.perBankRdBursts::3 1028 # Per bank write bursts
system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts
system.physmem.perBankRdBursts::5 1113 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts
system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::6 1087 # Per bank write bursts
system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts
system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61589097000 # Total gap between requests system.physmem.totGap 61594044000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 15575 # Read request sizes (log2) system.physmem.readPktSize::6 15574 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
system.physmem.totQLat 76265750 # Total ticks spent queuing system.physmem.totQLat 76216750 # Total ticks spent queuing
system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14017 # Number of row buffer hits during reads system.physmem.readRowHits 14024 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3954356.15 # Average gap between requests system.physmem.avgGap 3954927.70 # Average gap between requests
system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ) system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.598278 # Core power per rank (mW) system.physmem_0.averagePower 671.614039 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ) system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ) system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ) system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.510839 # Core power per rank (mW) system.physmem_1.averagePower 671.506960 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20789992 # Number of BP lookups system.cpu.branchPred.lookups 20791997 # Number of BP lookups
system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 123178383 # number of cpu cycles simulated system.cpu.numCycles 123188277 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359542 # CPI: cycles per instruction system.cpu.cpi 1.359651 # CPI: cycles per instruction
system.cpu.ipc 0.735542 # IPC: instructions per cycle system.cpu.ipc 0.735483 # IPC: instructions per cycle
system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946107 # number of replacements system.cpu.dcache.tags.replacements 946088 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits
system.cpu.dcache.overall_hits::total 26259880 # number of overall hits system.cpu.dcache.overall_hits::total 26259934 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74169 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74169 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989103 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989103 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989107 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses
system.cpu.dcache.overall_misses::total 989107 # number of overall misses system.cpu.dcache.overall_misses::total 989096 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918328994 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918328994 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566867500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2566867500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14485196494 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14485196494 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14485196494 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14485196494 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513494 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27248475 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248475 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27248987 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27248987 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14644.780669 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14644.721445 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks
system.cpu.dcache.writebacks::total 943285 # number of writebacks system.cpu.dcache.writebacks::total 943266 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27402 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27402 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38903 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38903 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38903 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38903 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950200 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950200 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413180006 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413180006 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1463830500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1463830500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877010506 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11877010506 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877166006 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877166006 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency
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system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
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system.cpu.icache.overall_avg_miss_latency::total 75689.597758 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency
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@ -587,123 +587,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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system.cpu.icache.overall_mshr_miss_latency::total 59238753 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency
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system.cpu.l2cache.overall_miss_latency::cpu.inst 58173250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1095558000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1153731250 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943285 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943285 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74772.814910 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84988.549618 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77346.394231 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73796.135864 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73796.135864 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74033.062757 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -721,104 +721,104 @@ system.cpu.l2cache.demand_mshr_hits::total 9 #
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48299750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18668000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66967750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891481000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891481000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48299750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910149000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 958448750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48299750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910149000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 958448750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943285 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843691 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845297 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183232 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadReq 1030 # Transaction distribution
system.membus.trans_dist::ReadResp 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 15575 # Request fanout histogram system.membus.snoop_fanout::samples 15574 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram
system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

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tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
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tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
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1612
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
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84
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
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@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.279362 # Number of seconds simulated sim_seconds 0.279362 # Number of seconds simulated
sim_ticks 279362297500 # Number of ticks simulated sim_ticks 279362298000 # Number of ticks simulated
final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1941586 # Simulator instruction rate (inst/s) host_inst_rate 1382525 # Simulator instruction rate (inst/s)
host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s) host_op_rate 1497457 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1070717412 # Simulator tick rate (ticks/s) host_tick_rate 762414599 # Simulator tick rate (ticks/s)
host_mem_usage 304560 # Number of bytes of host memory used host_mem_usage 298924 # Number of bytes of host memory used
host_seconds 260.91 # Real time elapsed on the host host_seconds 366.42 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated sim_insts 506581608 # Number of instructions simulated
sim_ops 548694828 # Number of ops (including micro ops) simulated sim_ops 548694829 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2066445504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory
system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory system.physmem.bytes_read::total 2489298205 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 2066445504 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 2066445504 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 516611376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory
system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory system.physmem.num_reads::total 632202903 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 7397009256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1513635534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 8910644789 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7397009256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7397009256 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 773431582 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 773431582 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7397009256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076371 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 558724596 # number of cpu cycles simulated system.cpu.numCycles 558724597 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506581607 # Number of instructions committed system.cpu.committedInsts 506581608 # Number of instructions committed
system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.committedOps 548694829 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured system.cpu.num_func_calls 19311615 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 749039746 # nu
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read system.cpu.num_cc_register_reads 1634230250 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
system.cpu.num_mem_refs 172745235 # number of memory refs system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 558724595.998000 # Number of busy cycles system.cpu.num_busy_cycles 558724596.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548301 # Number of branches fetched system.cpu.Branches 121548302 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Cl
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction
system.membus.trans_dist::ReadReq 630711790 # Transaction distribution system.membus.trans_dist::ReadReq 630711791 # Transaction distribution
system.membus.trans_dist::ReadResp 632200331 # Transaction distribution system.membus.trans_dist::ReadResp 632200332 # Transaction distribution
system.membus.trans_dist::WriteReq 54239306 # Transaction distribution system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
system.membus.trans_dist::WriteResp 54239306 # Transaction distribution system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 2571 # Tr
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222752 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1375861500 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 687930749 # Request fanout histogram system.membus.snoop_fanout::samples 687930750 # Request fanout histogram
system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram
system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 516611376 75.10% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.membus.snoop_fanout::total 687930750 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

318
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.707538 # Number of seconds simulated sim_seconds 0.707538 # Number of seconds simulated
sim_ticks 707538046500 # Number of ticks simulated sim_ticks 707538047500 # Number of ticks simulated
final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1058036 # Simulator instruction rate (inst/s) host_inst_rate 813114 # Simulator instruction rate (inst/s)
host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s) host_op_rate 880566 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1482416058 # Simulator tick rate (ticks/s) host_tick_rate 1139256199 # Simulator tick rate (ticks/s)
host_mem_usage 313032 # Number of bytes of host memory used host_mem_usage 308656 # Number of bytes of host memory used
host_seconds 477.29 # Real time elapsed on the host host_seconds 621.05 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated sim_insts 504986854 # Number of instructions simulated
sim_ops 546878104 # Number of ops (including micro ops) simulated sim_ops 546878105 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory
system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory
system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory
system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 1415076093 # number of cpu cycles simulated system.cpu.numCycles 1415076095 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 504986853 # Number of instructions committed system.cpu.committedInsts 504986854 # Number of instructions committed
system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 19311615 # number of times a function call or return occured system.cpu.num_func_calls 19311615 # number of times a function call or return occured
@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 748355652 # nu
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
system.cpu.num_mem_refs 172745235 # number of memory refs system.cpu.num_mem_refs 172745235 # number of memory refs
system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_load_insts 115884756 # Number of load instructions
system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_store_insts 56860479 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 121548301 # Number of branches fetched system.cpu.Branches 121548302 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Cl
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction
system.cpu.dcache.tags.replacements 1134822 # number of replacements system.cpu.dcache.tags.replacements 1134822 # number of replacements
system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979096000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 18979096000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979149500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.replacements 9788 # number of replacements
system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 983.372130 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 983.372130 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
@ -363,44 +363,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 24
system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits
system.cpu.icache.overall_hits::total 516599855 # number of overall hits system.cpu.icache.overall_hits::total 516599856 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
system.cpu.icache.overall_misses::total 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 266251500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 266251500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 266251500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 266251500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 266251500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 266251500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112178000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665547500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112178000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665547500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049940 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution

716
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.216865 # Number of seconds simulated sim_seconds 0.216744 # Number of seconds simulated
sim_ticks 216864820000 # Number of ticks simulated sim_ticks 216744260000 # Number of ticks simulated
final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 114758 # Simulator instruction rate (inst/s) host_inst_rate 123383 # Simulator instruction rate (inst/s)
host_op_rate 137779 # Simulator op (including micro ops) rate (op/s) host_op_rate 148134 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 91148248 # Simulator tick rate (ticks/s) host_tick_rate 97944157 # Simulator tick rate (ticks/s)
host_mem_usage 250616 # Number of bytes of host memory used host_mem_usage 314844 # Number of bytes of host memory used
host_seconds 2379.25 # Real time elapsed on the host host_seconds 2212.94 # Real time elapsed on the host
sim_insts 273037856 # Number of instructions simulated sim_insts 273037857 # Number of instructions simulated
sim_ops 327812213 # Number of ops (including micro ops) simulated sim_ops 327812214 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 218944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory
system.physmem.bytes_read::total 485376 # Number of bytes read from this memory system.physmem.bytes_read::total 485312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 218944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 218944 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 3421 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1010149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1228951 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2239100 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1010149 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1010149 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1010149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1228951 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2239100 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7584 # Number of read requests accepted system.physmem.readReqs 7583 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -46,8 +46,8 @@ system.physmem.perBankRdBursts::1 843 # Pe
system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::2 628 # Per bank write bursts
system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts
system.physmem.perBankRdBursts::4 466 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts
system.physmem.perBankRdBursts::5 349 # Per bank write bursts system.physmem.perBankRdBursts::5 348 # Per bank write bursts
system.physmem.perBankRdBursts::6 172 # Per bank write bursts system.physmem.perBankRdBursts::6 173 # Per bank write bursts
system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts
system.physmem.perBankRdBursts::8 209 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts
system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::9 311 # Per bank write bursts
@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 428 # Pe
system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts
system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts
system.physmem.perBankRdBursts::14 637 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts
system.physmem.perBankRdBursts::15 541 # Per bank write bursts system.physmem.perBankRdBursts::15 540 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 216864583500 # Total gap between requests system.physmem.totGap 216744023500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7584 # Read request sizes (log2) system.physmem.readPktSize::6 7583 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 318.314681 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 188.160813 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 331.826555 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 551 36.27% 36.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 356 23.44% 59.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 165 10.86% 70.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 80 5.27% 75.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 68 4.48% 80.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 50 3.29% 83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 36 2.37% 85.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 26 1.71% 87.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 187 12.31% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
system.physmem.totQLat 53624000 # Total ticks spent queuing system.physmem.totQLat 54921500 # Total ticks spent queuing
system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 197102750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst system.physmem.avgQLat 7242.71 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 25992.71 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6058 # Number of row buffer hits during reads system.physmem.readRowHits 6057 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28595013.65 # Average gap between requests system.physmem.avgGap 28582885.86 # Average gap between requests
system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 5639665500 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 125095914000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ) system.physmem_0.totalEnergy 144929531385 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.696011 # Core power per rank (mW) system.physmem_0.averagePower 668.684406 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states system.physmem_0.memoryStateTime::IDLE 208108813000 # Time in different power states
system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::REF 7237360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states system.physmem_0.memoryStateTime::ACT 1394961500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) system.physmem_1.actEnergy 6433560 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) system.physmem_1.preEnergy 3510375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.readEnergy 28984800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 14156276160 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 5856004440 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 124906143000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ) system.physmem_1.totalEnergy 144957352335 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.795085 # Core power per rank (mW) system.physmem_1.averagePower 668.812768 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states system.physmem_1.memoryStateTime::IDLE 207790968250 # Time in different power states
system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::REF 7237360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states system.physmem_1.memoryStateTime::ACT 1713539250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 33219593 # Number of BP lookups system.cpu.branchPred.lookups 33185861 # Number of BP lookups
system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 17151464 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 1557357 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups system.cpu.branchPred.BTBLookups 17401044 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBHits 15621725 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 89.774642 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 6610647 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 433729640 # number of cpu cycles simulated system.cpu.numCycles 433488520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedInsts 273037857 # Number of instructions committed
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 4013329 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.588533 # CPI: cycles per instruction system.cpu.cpi 1.587650 # CPI: cycles per instruction
system.cpu.ipc 0.629512 # IPC: instructions per cycle system.cpu.ipc 0.629862 # IPC: instructions per cycle
system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked system.cpu.tickCycles 429966989 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 3521531 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1354 # number of replacements system.cpu.dcache.tags.replacements 1354 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3085.753926 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 168769445 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 37412.867435 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3085.753926 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.753358 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753358 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
@ -404,54 +404,54 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 337557971 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses system.cpu.dcache.tags.data_accesses 337557971 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 86636657 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86636657 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63541 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63541 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 168684114 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 168684114 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 168747655 # number of overall hits
system.cpu.dcache.overall_hits::total 168760431 # number of overall hits system.cpu.dcache.overall_hits::total 168747655 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 7279 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7279 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 7285 # number of overall misses
system.cpu.dcache.overall_misses::total 7284 # number of overall misses system.cpu.dcache.overall_misses::total 7285 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 137443456 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 137443456 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 400907250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 400907250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 538350706 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 538350706 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 538350706 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 538350706 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 86638716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86638716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63547 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 63547 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 168691393 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 168691393 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 168754940 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 168754940 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66752.528412 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 66752.528412 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76802.155172 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 76802.155172 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 73959.432065 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 73959.432065 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 73898.518325 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 73898.518325 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu
system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2772 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2772 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2772 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 2772 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4507
system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109995542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 109995542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220772750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 220772750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330768292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 330768292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331089042 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 331089042 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -518,71 +518,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67193.367135 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67193.367135 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76924.303136 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76924.303136 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73389.902818 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 73389.902818 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73395.930392 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 73395.930392 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 36897 # number of replacements system.cpu.icache.tags.replacements 36918 # number of replacements
system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1924.846019 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 73120141 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 38855 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 1881.872114 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1924.846019 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.939866 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939866 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1490 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses system.cpu.icache.tags.tag_accesses 146356849 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses system.cpu.icache.tags.data_accesses 146356849 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 73120141 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 73120141 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 73120141 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 73120141 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 73120141 # number of overall hits
system.cpu.icache.overall_hits::total 73252007 # number of overall hits system.cpu.icache.overall_hits::total 73120141 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 38856 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 38856 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 38856 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 38856 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 38856 # number of overall misses
system.cpu.icache.overall_misses::total 38835 # number of overall misses system.cpu.icache.overall_misses::total 38856 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 728255248 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 728255248 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 728255248 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 728255248 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 728255248 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 728255248 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 73158997 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 73158997 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 73158997 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 73158997 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 73158997 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 73158997 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18742.414247 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 18742.414247 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 18742.414247 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18742.414247 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 18742.414247 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -591,123 +591,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38856 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 38856 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 38856 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 38856 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 38856 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 38856 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668686502 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668527252 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 668686502 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 668527252 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668686502 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668527252 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 668686502 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 668527252 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668686502 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668527252 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 668686502 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 668527252 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17205.251493 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17205.251493 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17205.251493 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17205.251493 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4197.194738 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 4198.154832 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 35803 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5645 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 6.342427 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 353.722054 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 353.729151 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177954 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.134287 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294730 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 678.291394 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096623 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.128118 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 5645 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172272 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 363531 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses system.cpu.l2cache.tags.data_accesses 363531 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 35433 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 35724 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 35433 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 35740 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 35433 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
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system.cpu.l2cache.overall_avg_miss_latency::total 76027.923440 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 76169.365412 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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@ -725,104 +725,104 @@ system.cpu.l2cache.demand_mshr_hits::total 44 #
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116774 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088043 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.174856 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62749.123063 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66141.628440 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63687.460351 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63769.358795 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63769.358795 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62749.123063 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64514.896684 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63718.284320 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 40497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 40496 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77711 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 87743 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486720 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 59005248 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 4730 # Transaction distribution system.membus.trans_dist::ReadReq 4729 # Transaction distribution
system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadResp 4729 # Transaction distribution
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7584 # Request fanout histogram system.membus.snoop_fanout::samples 7583 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7584 # Request fanout histogram system.membus.snoop_fanout::total 7583 # Request fanout histogram
system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 8950500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 40258250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

1218
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
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84
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
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@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.201717 # Number of seconds simulated sim_seconds 0.201717 # Number of seconds simulated
sim_ticks 201717313500 # Number of ticks simulated sim_ticks 201717314000 # Number of ticks simulated
final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1235958 # Simulator instruction rate (inst/s) host_inst_rate 854590 # Simulator instruction rate (inst/s)
host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s) host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 913112758 # Simulator tick rate (ticks/s) host_tick_rate 631341281 # Simulator tick rate (ticks/s)
host_mem_usage 308700 # Number of bytes of host memory used host_mem_usage 304088 # Number of bytes of host memory used
host_seconds 220.91 # Real time elapsed on the host host_seconds 319.51 # Real time elapsed on the host
sim_insts 273037594 # Number of instructions simulated sim_insts 273037595 # Number of instructions simulated
sim_ops 327811949 # Number of ops (including micro ops) simulated sim_ops 327811950 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 403434628 # number of cpu cycles simulated system.cpu.numCycles 403434629 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037594 # Number of instructions committed system.cpu.committedInsts 273037595 # Number of instructions committed
system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured system.cpu.num_func_calls 12448615 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 1174407516 # nu
system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
system.cpu.num_mem_refs 168107829 # number of memory refs system.cpu.num_mem_refs 168107829 # number of memory refs
system.cpu.num_load_insts 85732235 # Number of load instructions system.cpu.num_load_insts 85732235 # Number of load instructions
system.cpu.num_store_insts 82375594 # Number of store instructions system.cpu.num_store_insts 82375594 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 403434627.998000 # Number of busy cycles system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563490 # Number of branches fetched system.cpu.Branches 30563491 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Cl
system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812144 # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction
system.membus.trans_dist::ReadReq 434895827 # Transaction distribution system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
system.membus.trans_dist::ReadResp 434906722 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
system.membus.trans_dist::WriteResp 82052672 # Transaction distribution system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 54062 # Tr
system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 517024351 # Request fanout histogram system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram
system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 517024351 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

308
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.517235 # Number of seconds simulated sim_seconds 0.517235 # Number of seconds simulated
sim_ticks 517235404500 # Number of ticks simulated sim_ticks 517235405500 # Number of ticks simulated
final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 517235405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 693666 # Simulator instruction rate (inst/s) host_inst_rate 520716 # Simulator instruction rate (inst/s)
host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) host_op_rate 625139 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1315500911 # Simulator tick rate (ticks/s) host_tick_rate 987510163 # Simulator tick rate (ticks/s)
host_mem_usage 318184 # Number of bytes of host memory used host_mem_usage 313820 # Number of bytes of host memory used
host_seconds 393.19 # Real time elapsed on the host host_seconds 523.78 # Real time elapsed on the host
sim_insts 272739285 # Number of instructions simulated sim_insts 272739286 # Number of instructions simulated
sim_ops 327433743 # Number of ops (including micro ops) simulated sim_ops 327433744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1034470809 # number of cpu cycles simulated system.cpu.numCycles 1034470811 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 272739285 # Number of instructions committed system.cpu.committedInsts 272739286 # Number of instructions committed
system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12448615 # number of times a function call or return occured system.cpu.num_func_calls 12448615 # number of times a function call or return occured
@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 1215888421 # nu
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
system.cpu.num_mem_refs 168107847 # number of memory refs system.cpu.num_mem_refs 168107847 # number of memory refs
system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_load_insts 85732248 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles system.cpu.num_busy_cycles 1034470810.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 30563502 # Number of branches fetched system.cpu.Branches 30563503 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Cl
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction
system.cpu.dcache.tags.replacements 1332 # number of replacements system.cpu.dcache.tags.replacements 1332 # number of replacements
system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3078.445034 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445034 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 235818500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 235818500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 235818500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 235818500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.098302 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 52685.098302 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 52649.810225 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 52649.810225 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75951500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 75951500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229066000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 229066000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229226500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 229226500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47380.848409 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47380.848409 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51187.932961 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 51187.932961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51189.481912 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51189.481912 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.replacements 13796 # number of replacements
system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1766.007655 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007655 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
@ -362,44 +362,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
system.cpu.icache.overall_hits::total 348644749 # number of overall hits system.cpu.icache.overall_hits::total 348644750 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
system.cpu.icache.overall_misses::total 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 312482000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 312482000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 312482000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 312482000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 312482000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 312482000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
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@ -533,48 +533,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105625000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55404000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105625000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171072000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105625000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171072000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383436 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383436 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

840
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
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1627
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
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84
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
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@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.395727 # Number of seconds simulated sim_seconds 0.395727 # Number of seconds simulated
sim_ticks 395726778000 # Number of ticks simulated sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1601804 # Simulator instruction rate (inst/s) host_inst_rate 1109777 # Simulator instruction rate (inst/s)
host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s) host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 989420456 # Simulator tick rate (ticks/s) host_tick_rate 685499869 # Simulator tick rate (ticks/s)
host_mem_usage 309588 # Number of bytes of host memory used host_mem_usage 303676 # Number of bytes of host memory used
host_seconds 399.96 # Real time elapsed on the host host_seconds 577.28 # Real time elapsed on the host
sim_insts 640654410 # Number of instructions simulated sim_insts 640654411 # Number of instructions simulated
sim_ops 788730069 # Number of ops (including micro ops) simulated sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 791453557 # number of cpu cycles simulated system.cpu.numCycles 791453558 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640654410 # Number of instructions committed system.cpu.committedInsts 640654411 # Number of instructions committed
system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured system.cpu.num_func_calls 37261296 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 1320162254 # nu
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 791453556.998000 # Number of busy cycles system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364859 # Number of branches fetched system.cpu.Branches 137364860 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Cl
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730743 # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction
system.membus.trans_dist::ReadReq 893703777 # Transaction distribution system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
system.membus.trans_dist::ReadResp 893709516 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
system.membus.trans_dist::WriteResp 128951477 # Transaction distribution system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 3620 # Tr
system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram
system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 1022670352 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

308
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 1.043695 # Number of seconds simulated sim_seconds 1.043695 # Number of seconds simulated
sim_ticks 1043695077500 # Number of ticks simulated sim_ticks 1043695078500 # Number of ticks simulated
final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 1043695078500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 877071 # Simulator instruction rate (inst/s) host_inst_rate 624059 # Simulator instruction rate (inst/s)
host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) host_op_rate 766694 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1431720298 # Simulator tick rate (ticks/s) host_tick_rate 1018706197 # Simulator tick rate (ticks/s)
host_mem_usage 317788 # Number of bytes of host memory used host_mem_usage 313408 # Number of bytes of host memory used
host_seconds 728.98 # Real time elapsed on the host host_seconds 1024.53 # Real time elapsed on the host
sim_insts 639366786 # Number of instructions simulated sim_insts 639366787 # Number of instructions simulated
sim_ops 785501034 # Number of ops (including micro ops) simulated sim_ops 785501035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18428352 # Number of bytes read from this memory
system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 287943 # Number of read requests responded to by this memory
system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 108476 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 17656835 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 108476 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 108476 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 108476 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17656835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.numCycles 2087390155 # number of cpu cycles simulated system.cpu.numCycles 2087390157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 639366786 # Number of instructions committed system.cpu.committedInsts 639366787 # Number of instructions committed
system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
system.cpu.num_func_calls 37261296 # number of times a function call or return occured system.cpu.num_func_calls 37261296 # number of times a function call or return occured
@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 1323974869 # nu
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
system.cpu.num_mem_refs 381221435 # number of memory refs system.cpu.num_mem_refs 381221435 # number of memory refs
system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_load_insts 252240938 # Number of load instructions
system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_store_insts 128980497 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles system.cpu.num_busy_cycles 2087390156.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 137364859 # Number of branches fetched system.cpu.Branches 137364860 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Cl
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 788730743 # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction
system.cpu.dcache.tags.replacements 778046 # number of replacements system.cpu.dcache.tags.replacements 778046 # number of replacements
system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 4093.640584 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 996415000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640584 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
system.cpu.dcache.overall_misses::total 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582740000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 18582740000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 22259892000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 22259892000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 22259892000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 22259892000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.414780 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.414780 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.189436 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 28465.189436 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.130692 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 28460.130692 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513680000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513680000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086847500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 21086847500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088530000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 21088530000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.395241 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.395241 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.174686 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.174686 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.533658 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.533658 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.replacements 8769 # number of replacements
system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1391.464501 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464501 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
@ -367,44 +367,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 43
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits
system.cpu.icache.overall_hits::total 643367691 # number of overall hits system.cpu.icache.overall_hits::total 643367692 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
system.cpu.icache.overall_misses::total 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 207074000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 207074000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 207074000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 207074000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 207074000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 207074000 # number of overall miss cycles
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system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
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system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20285.462382 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 20285.462382 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 20285.462382 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 20285.462382 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 20285.462382 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -419,37 +419,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 191762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 191762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191762000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 191762000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18785.462382 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18785.462382 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18785.462382 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18785.462382 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 256932 # number of replacements system.cpu.l2cache.tags.replacements 256932 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 32626.698157 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505444 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.076488 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.116225 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.908970 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
@ -460,40 +460,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 8438 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 8439 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 91561 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
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@ -508,27 +508,27 @@ system.cpu.l2cache.demand_accesses::total 792350 # n
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.700961 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010617 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@ -540,48 +540,48 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1770 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1769 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221849 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221850 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 223619 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1770 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 287942 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 287943 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 289712 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 287943 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71648500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984925000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71648500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661691500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71648500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661691500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311229 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368147 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.261164 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.261164 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

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tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
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@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.832017 # Number of seconds simulated sim_seconds 0.832017 # Number of seconds simulated
sim_ticks 832017490000 # Number of ticks simulated sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1937211 # Simulator instruction rate (inst/s) host_inst_rate 1379227 # Simulator instruction rate (inst/s)
host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s) host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1043527090 # Simulator tick rate (ticks/s) host_tick_rate 742955189 # Simulator tick rate (ticks/s)
host_mem_usage 301332 # Number of bytes of host memory used host_mem_usage 295688 # Number of bytes of host memory used
host_seconds 797.31 # Real time elapsed on the host host_seconds 1119.88 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032433 # Number of ops (including micro ops) simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1664034981 # number of cpu cycles simulated system.cpu.numCycles 1664034982 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563041 # Number of instructions committed system.cpu.committedInsts 1544563042 # Number of instructions committed
system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured system.cpu.num_func_calls 27330256 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 2605402942 # nu
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 1664034980.998000 # Number of busy cycles system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched system.cpu.Branches 213462427 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Cl
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction
system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 1 # Tr
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram
system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 2172060894 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

80
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 2.363663 # Number of seconds simulated sim_seconds 2.363663 # Number of seconds simulated
sim_ticks 2363662966500 # Number of ticks simulated sim_ticks 2363662967500 # Number of ticks simulated
final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2363662967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1021163 # Simulator instruction rate (inst/s) host_inst_rate 734295 # Simulator instruction rate (inst/s)
host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s) host_op_rate 791306 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1568591191 # Simulator tick rate (ticks/s) host_tick_rate 1127938114 # Simulator tick rate (ticks/s)
host_mem_usage 309800 # Number of bytes of host memory used host_mem_usage 305424 # Number of bytes of host memory used
host_seconds 1506.87 # Real time elapsed on the host host_seconds 2095.56 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated sim_insts 1538759602 # Number of instructions simulated
sim_ops 1658228914 # Number of ops (including micro ops) simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4727325933 # number of cpu cycles simulated system.cpu.numCycles 4727325935 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759601 # Number of instructions committed system.cpu.committedInsts 1538759602 # Number of instructions committed
system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured system.cpu.num_func_calls 27330256 # number of times a function call or return occured
@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 2601860372 # nu
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles system.cpu.num_busy_cycles 4727325934.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched system.cpu.Branches 213462427 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Cl
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction
system.cpu.dcache.tags.replacements 9111140 # number of replacements system.cpu.dcache.tags.replacements 9111140 # number of replacements
system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 4083.733673 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 25164659000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733673 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -347,9 +347,9 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.replacements 7 # number of replacements
system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
@ -359,14 +359,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 24
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
system.cpu.icache.overall_hits::total 1544564952 # number of overall hits system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
@ -379,12 +379,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 34207000
system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
@ -431,14 +431,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461
system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1926075 # number of replacements system.cpu.l2cache.tags.replacements 1926075 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 31008.535032 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 150067843000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160482 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498452 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy

642
tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.131756 # Number of seconds simulated sim_seconds 0.131767 # Number of seconds simulated
sim_ticks 131756455500 # Number of ticks simulated sim_ticks 131767151500 # Number of ticks simulated
final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 150043 # Simulator instruction rate (inst/s) host_inst_rate 176753 # Simulator instruction rate (inst/s)
host_op_rate 158169 # Simulator op (including micro ops) rate (op/s) host_op_rate 186327 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 114724713 # Simulator tick rate (ticks/s) host_tick_rate 135158895 # Simulator tick rate (ticks/s)
host_mem_usage 245376 # Number of bytes of host memory used host_mem_usage 309748 # Number of bytes of host memory used
host_seconds 1148.46 # Real time elapsed on the host host_seconds 974.91 # Real time elapsed on the host
sim_insts 172317809 # Number of instructions simulated sim_insts 172317810 # Number of instructions simulated
sim_ops 181650742 # Number of ops (including micro ops) simulated sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 138304 # Nu
system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 1049609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 829585 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 1879194 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1049609 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1049609 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1049609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 829585 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1879194 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.readReqs 3869 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
@ -52,11 +52,11 @@ system.physmem.perBankRdBursts::7 222 # Pe
system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts
system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts
system.physmem.perBankRdBursts::10 295 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts
system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::11 200 # Per bank write bursts
system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts
system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts
system.physmem.perBankRdBursts::14 224 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts
system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankRdBursts::15 205 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 131756361000 # Total gap between requests system.physmem.totGap 131767057000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 907 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 272.793826 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 180.627814 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 276.033343 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 260 28.67% 28.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 352 38.81% 67.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 83 9.15% 76.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 54 5.95% 82.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 42 4.63% 87.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 20 2.21% 89.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 22 2.43% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 19 2.09% 93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 55 6.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 907 # Bytes accessed per row activation
system.physmem.totQLat 26795500 # Total ticks spent queuing system.physmem.totQLat 28218000 # Total ticks spent queuing
system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 100761750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst system.physmem.avgQLat 7293.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 26043.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
@ -216,49 +216,49 @@ system.physmem.busUtilRead 0.01 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.readRowHits 2961 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34054370.90 # Average gap between requests system.physmem.avgGap 34057135.44 # Average gap between requests
system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 3114720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 1699500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 16200600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 3598001595 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 75904039500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ) system.physmem_0.totalEnergy 88129416795 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.773046 # Core power per rank (mW) system.physmem_0.averagePower 668.827838 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states system.physmem_0.memoryStateTime::IDLE 126271035750 # Time in different power states
system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::REF 4399980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states system.physmem_0.memoryStateTime::ACT 1095966750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) system.physmem_1.actEnergy 3742200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) system.physmem_1.preEnergy 2041875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.readEnergy 13954200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) system.physmem_1.refreshEnergy 8606360880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) system.physmem_1.actBackEnergy 3577878315 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 75921691500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) system.physmem_1.totalEnergy 88125668970 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.806861 # Core power per rank (mW) system.physmem_1.averagePower 668.799395 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states system.physmem_1.memoryStateTime::IDLE 126300767500 # Time in different power states
system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::REF 4399980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT 1066235000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 49934475 # Number of BP lookups system.cpu.branchPred.lookups 49934214 # Number of BP lookups
system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 39669228 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 5745476 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups system.cpu.branchPred.BTBLookups 24397430 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBHits 23302007 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 95.510089 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 1908013 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numCycles 263534303 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedInsts 172317810 # Number of instructions committed
system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 11762366 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.529226 # CPI: cycles per instruction system.cpu.cpi 1.529350 # CPI: cycles per instruction
system.cpu.ipc 0.653925 # IPC: instructions per cycle system.cpu.ipc 0.653872 # IPC: instructions per cycle
system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked system.cpu.tickCycles 257146871 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 6387432 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 1377.696434 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 40764379 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 22521.756354 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 1377.696434 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 81535444 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses system.cpu.dcache.tags.data_accesses 81535444 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 28356460 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28356460 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 40719101 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 40719101 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 40719565 # number of overall hits
system.cpu.dcache.overall_hits::total 40720862 # number of overall hits system.cpu.dcache.overall_hits::total 40719565 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses system.cpu.dcache.demand_misses::cpu.data 2437 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2437 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 2438 # number of overall misses
system.cpu.dcache.overall_misses::total 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2438 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 59434234 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 59434234 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 127677000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 127677000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 187111234 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 187111234 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 187111234 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 187111234 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 28357251 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 28357251 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 40721538 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 40721538 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 40722003 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 40722003 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75138.096081 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75138.096081 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77568.043742 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 77568.043742 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 76779.332786 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 76779.332786 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 76747.840033 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 76747.840033 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 628 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 628 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 628 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52911264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 52911264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85210500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 85210500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138121764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 138121764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138191264 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 138191264 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74418.092827 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74418.092827 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77605.191257 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77605.191257 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76352.550580 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 76352.550580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76348.764641 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76348.764641 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 2891 # number of replacements system.cpu.icache.tags.replacements 2892 # number of replacements
system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1425.992142 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 71598587 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 4690 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 15266.223241 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1425.992142 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.696285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.696285 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses system.cpu.icache.tags.tag_accesses 143211246 # Number of tag accesses
system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses system.cpu.icache.tags.data_accesses 143211246 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 71598587 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 71598587 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 71598587 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 71598587 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 71598587 # number of overall hits
system.cpu.icache.overall_hits::total 71597353 # number of overall hits system.cpu.icache.overall_hits::total 71598587 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 4691 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 4691 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 4691 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 4691 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 4691 # number of overall misses
system.cpu.icache.overall_misses::total 4689 # number of overall misses system.cpu.icache.overall_misses::total 4691 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 200040248 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 200040248 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 200040248 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 200040248 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 200040248 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 200040248 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 71603278 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 71603278 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 71603278 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 71603278 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 71603278 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 71603278 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.412492 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 42643.412492 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 42643.412492 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.412492 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 42643.412492 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -591,66 +591,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514529 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.595293 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460883 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.595293 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61824.468085 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68751.618123 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63364.388489 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64585.321101 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64585.321101 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61824.468085 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66092.798595 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63708.268734 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 5403 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5402 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9381 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 13017 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 7498748 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 3019736 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 2779 # Transaction distribution system.membus.trans_dist::ReadReq 2779 # Transaction distribution
system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadResp 2779 # Transaction distribution
@ -820,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 3869 # Request fanout histogram system.membus.snoop_fanout::total 3869 # Request fanout histogram
system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 4517000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 20556500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

1248
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
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434
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
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@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated sim_seconds 0.000030 # Number of seconds simulated
sim_ticks 30427500 # Number of ticks simulated sim_ticks 30321500 # Number of ticks simulated
final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 90683 # Simulator instruction rate (inst/s) host_inst_rate 50258 # Simulator instruction rate (inst/s)
host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) host_op_rate 58824 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 599001910 # Simulator tick rate (ticks/s) host_tick_rate 330783185 # Simulator tick rate (ticks/s)
host_mem_usage 308040 # Number of bytes of host memory used host_mem_usage 302404 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host host_seconds 0.09 # Real time elapsed on the host
sim_insts 4604 # Number of instructions simulated sim_insts 4605 # Number of instructions simulated
sim_ops 5390 # Number of ops (including micro ops) simulated sim_ops 5391 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 30336000 # Total gap between requests system.physmem.totGap 30230000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -187,50 +187,50 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 286.758489 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation system.physmem.bytesPerActivate::stdev 323.986232 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
system.physmem.totQLat 2605000 # Total ticks spent queuing system.physmem.totQLat 2532750 # Total ticks spent queuing
system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 6.92 # Data bus utilization in percentage system.physmem.busUtil 6.94 # Data bus utilization in percentage
system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.readRowHits 349 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 72057.01 # Average gap between requests system.physmem.avgGap 71805.23 # Average gap between requests
system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ)
system.physmem_0.averagePower 848.018629 # Core power per rank (mW) system.physmem_0.averagePower 848.348875 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
@ -245,19 +245,19 @@ system.physmem_1.actBackEnergy 15437025 # En
system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ)
system.physmem_1.averagePower 782.664197 # Core power per rank (mW) system.physmem_1.averagePower 782.664197 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states system.physmem_1.memoryStateTime::IDLE 2433750 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1927 # Number of BP lookups system.cpu.branchPred.lookups 1918 # Number of BP lookups
system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect system.cpu.branchPred.condIncorrect 336 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups system.cpu.branchPred.BTBLookups 1604 # Number of BTB lookups
system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBHits 341 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage system.cpu.branchPred.BTBHitPct 21.259352 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 60855 # number of cpu cycles simulated system.cpu.numCycles 60643 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedInsts 4605 # Number of instructions committed
system.cpu.committedOps 5390 # Number of ops (including micro ops) committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 13.217854 # CPI: cycles per instruction system.cpu.cpi 13.168947 # CPI: cycles per instruction
system.cpu.ipc 0.075655 # IPC: instructions per cycle system.cpu.ipc 0.075936 # IPC: instructions per cycle
system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked
system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits
system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.overall_hits::total 1895 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4806 # Number of data accesses system.cpu.icache.tags.data_accesses 4784 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits
system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.overall_hits::total 1909 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
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system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
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@ -573,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322
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system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use
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system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
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system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -698,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421
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system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses
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@ -720,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
@ -758,7 +758,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 #
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
@ -781,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 421 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram
system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.4 # Layer utilization (%) system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

1198
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
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934
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
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98
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
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@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2694500 # Number of ticks simulated sim_ticks 2695000 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 771856 # Simulator instruction rate (inst/s) host_inst_rate 88081 # Simulator instruction rate (inst/s)
host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) host_op_rate 103121 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 450886881 # Simulator tick rate (ticks/s) host_tick_rate 51657705 # Simulator tick rate (ticks/s)
host_mem_usage 297796 # Number of bytes of host memory used host_mem_usage 292672 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host host_seconds 0.05 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated sim_insts 4592 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
system.physmem.bytes_read::total 22907 # Number of bytes read from this memory system.physmem.bytes_read::total 22911 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -272,11 +272,11 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numCycles 5391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4591 # Number of instructions committed system.cpu.committedInsts 4592 # Number of instructions committed
system.cpu.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.committedOps 5378 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 203 # number of times a function call or return occured system.cpu.num_func_calls 203 # number of times a function call or return occured
@ -287,18 +287,18 @@ system.cpu.num_int_register_reads 7607 # nu
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched system.cpu.Branches 1008 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
@ -323,40 +323,40 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction
system.membus.trans_dist::ReadReq 5596 # Transaction distribution system.membus.trans_dist::ReadReq 5597 # Transaction distribution
system.membus.trans_dist::ReadResp 5607 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution
system.membus.trans_dist::WriteReq 913 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution
system.membus.trans_dist::WriteResp 913 # Transaction distribution system.membus.trans_dist::WriteResp 913 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
system.membus.trans_dist::StoreCondReq 11 # Transaction distribution system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
system.membus.trans_dist::StoreCondResp 11 # Transaction distribution system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6531 # Request fanout histogram system.membus.snoop_fanout::samples 6532 # Request fanout histogram
system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 6531 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

98
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2694500 # Number of ticks simulated sim_ticks 2695000 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 801222 # Simulator instruction rate (inst/s) host_inst_rate 99386 # Simulator instruction rate (inst/s)
host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) host_op_rate 116351 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 468120222 # Simulator tick rate (ticks/s) host_tick_rate 58281162 # Simulator tick rate (ticks/s)
host_mem_usage 297024 # Number of bytes of host memory used host_mem_usage 291652 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host host_seconds 0.05 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated sim_insts 4592 # Number of instructions simulated
sim_ops 5377 # Number of ops (including micro ops) simulated sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
system.physmem.bytes_read::total 22907 # Number of bytes read from this memory system.physmem.bytes_read::total 22911 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 5390 # number of cpu cycles simulated system.cpu.numCycles 5391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4591 # Number of instructions committed system.cpu.committedInsts 4592 # Number of instructions committed
system.cpu.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.committedOps 5378 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 203 # number of times a function call or return occured system.cpu.num_func_calls 203 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 7607 # nu
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched system.cpu.Branches 1008 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
@ -204,40 +204,40 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction
system.membus.trans_dist::ReadReq 5596 # Transaction distribution system.membus.trans_dist::ReadReq 5597 # Transaction distribution
system.membus.trans_dist::ReadResp 5607 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution
system.membus.trans_dist::WriteReq 913 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution
system.membus.trans_dist::WriteResp 913 # Transaction distribution system.membus.trans_dist::WriteResp 913 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
system.membus.trans_dist::StoreCondReq 11 # Transaction distribution system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
system.membus.trans_dist::StoreCondResp 11 # Transaction distribution system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6531 # Request fanout histogram system.membus.snoop_fanout::samples 6532 # Request fanout histogram
system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 6531 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

132
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.000026 # Number of seconds simulated sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 25815500 # Number of ticks simulated sim_ticks 25816500 # Number of ticks simulated
final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 263675 # Simulator instruction rate (inst/s) host_inst_rate 77759 # Simulator instruction rate (inst/s)
host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) host_op_rate 90742 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1488783160 # Simulator tick rate (ticks/s) host_tick_rate 439383785 # Simulator tick rate (ticks/s)
host_mem_usage 306760 # Number of bytes of host memory used host_mem_usage 301384 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host host_seconds 0.06 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated sim_insts 4566 # Number of instructions simulated
sim_ops 5329 # Number of ops (including micro ops) simulated sim_ops 5330 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numCycles 51633 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4565 # Number of instructions committed system.cpu.committedInsts 4566 # Number of instructions committed
system.cpu.committedOps 5329 # Number of ops (including micro ops) committed system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 203 # number of times a function call or return occured system.cpu.num_func_calls 203 # number of times a function call or return occured
@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 7573 # nu
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_mem_refs 1965 # number of memory refs
system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_load_insts 1027 # Number of load instructions
system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_store_insts 938 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 1007 # Number of branches fetched system.cpu.Branches 1008 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
@ -198,22 +198,22 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
@ -320,26 +320,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
system.cpu.icache.tags.data_accesses 9451 # Number of data accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
system.cpu.icache.overall_hits::total 4364 # number of overall hits system.cpu.icache.overall_hits::total 4365 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
@ -352,18 +352,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12588500
system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
@ -390,12 +390,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000
system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
@ -404,13 +404,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834
system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy

84
tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.054141 # Number of seconds simulated sim_seconds 0.054141 # Number of seconds simulated
sim_ticks 54141000000 # Number of ticks simulated sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1893120 # Simulator instruction rate (inst/s) host_inst_rate 1362402 # Simulator instruction rate (inst/s)
host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1131265211 # Simulator tick rate (ticks/s) host_tick_rate 814125846 # Simulator tick rate (ticks/s)
host_mem_usage 433636 # Number of bytes of host memory used host_mem_usage 428768 # Number of bytes of host memory used
host_seconds 47.86 # Real time elapsed on the host host_seconds 66.50 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated sim_insts 90602408 # Number of instructions simulated
sim_ops 91053638 # Number of ops (including micro ops) simulated sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108282001 # number of cpu cycles simulated system.cpu.numCycles 108282002 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602407 # Number of instructions committed system.cpu.committedInsts 90602408 # Number of instructions committed
system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured system.cpu.num_func_calls 112245 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 124257699 # nu
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732304 # Number of branches fetched system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Cl
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction
system.membus.trans_dist::ReadReq 130287905 # Transaction distribution system.membus.trans_dist::ReadReq 130287906 # Transaction distribution
system.membus.trans_dist::ReadResp 130291792 # Transaction distribution system.membus.trans_dist::ReadResp 130291793 # Transaction distribution
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
system.membus.trans_dist::WriteResp 4734981 # Transaction distribution system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
system.membus.trans_dist::SoftPFReq 510 # Transaction distribution system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 510 # Tr
system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031170 # Request fanout histogram system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 135031170 # Request fanout histogram system.membus.snoop_fanout::total 135031171 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

304
tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.147041 # Number of seconds simulated sim_seconds 0.147041 # Number of seconds simulated
sim_ticks 147041218500 # Number of ticks simulated sim_ticks 147041219500 # Number of ticks simulated
final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 147041219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 937429 # Simulator instruction rate (inst/s) host_inst_rate 770569 # Simulator instruction rate (inst/s)
host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) host_op_rate 774399 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1521808702 # Simulator tick rate (ticks/s) host_tick_rate 1250931150 # Simulator tick rate (ticks/s)
host_mem_usage 442868 # Number of bytes of host memory used host_mem_usage 437476 # Number of bytes of host memory used
host_seconds 96.62 # Real time elapsed on the host host_seconds 117.55 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated sim_insts 90576862 # Number of instructions simulated
sim_ops 91026990 # Number of ops (including micro ops) simulated sim_ops 91026991 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory
system.physmem.bytes_read::total 981760 # Number of bytes read from this memory system.physmem.bytes_read::total 981760 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 294082437 # number of cpu cycles simulated system.cpu.numCycles 294082439 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90576861 # Number of instructions committed system.cpu.committedInsts 90576862 # Number of instructions committed
system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured system.cpu.num_func_calls 112245 # number of times a function call or return occured
@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 124237033 # nu
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles system.cpu.num_busy_cycles 294082438.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732304 # Number of branches fetched system.cpu.Branches 18732305 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Cl
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction
system.cpu.dcache.tags.replacements 942702 # number of replacements system.cpu.dcache.tags.replacements 942702 # number of replacements
system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 3565.593917 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 54410415000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593917 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n
system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
system.cpu.dcache.overall_misses::total 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819
system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361087000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361087000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508357000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 11508357000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508475500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 11508475500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.940168 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.940168 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.067359 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.067359 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.154003 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.154003 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.replacements 2 # number of replacements
system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 510.120567 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 510.120567 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
@ -360,44 +360,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 6
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses
system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits
system.cpu.icache.overall_hits::total 107830172 # number of overall hits system.cpu.icache.overall_hits::total 107830173 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
system.cpu.icache.overall_misses::total 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 32032000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 32032000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 32032000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53475.792988 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 53475.792988 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 53475.792988 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 53475.792988 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -412,37 +412,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31133500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 31133500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31133500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 31133500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31133500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 31133500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51975.792988 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51975.792988 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 51975.792988 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51975.792988 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51975.792988 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 9567.852356 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446284 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172984 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233089 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
@ -453,40 +453,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses
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system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits
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@ -501,27 +501,27 @@ system.cpu.l2cache.demand_accesses::total 947397 # n
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.064125 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.302326 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.064125 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.064125 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@ -531,38 +531,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 577 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 215 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23368500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8707500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597901500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597901500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency

84
tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.048960 # Number of seconds simulated sim_seconds 0.048960 # Number of seconds simulated
sim_ticks 48960011000 # Number of ticks simulated sim_ticks 48960011500 # Number of ticks simulated
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1566427 # Simulator instruction rate (inst/s) host_inst_rate 1111911 # Simulator instruction rate (inst/s)
host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1081494789 # Simulator tick rate (ticks/s) host_tick_rate 767686935 # Simulator tick rate (ticks/s)
host_mem_usage 308080 # Number of bytes of host memory used host_mem_usage 303468 # Number of bytes of host memory used
host_seconds 45.27 # Real time elapsed on the host host_seconds 63.78 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated sim_insts 70913182 # Number of instructions simulated
sim_ops 90688136 # Number of ops (including micro ops) simulated sim_ops 90688137 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 312580276 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory
system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory system.physmem.bytes_read::total 419153621 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 312580276 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 312580276 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 78145069 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory system.physmem.num_reads::total 101064799 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 6384399562 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2176742646 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 8561142209 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 6384399562 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 6384399562 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1606621579 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1606621579 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 6384399562 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783364226 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763788 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 97920023 # number of cpu cycles simulated system.cpu.numCycles 97920024 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70913181 # Number of instructions committed system.cpu.committedInsts 70913182 # Number of instructions committed
system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.committedOps 90688137 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured system.cpu.num_func_calls 3311620 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 141479310 # nu
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read system.cpu.num_cc_register_reads 266608031 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles system.cpu.num_busy_cycles 97920023.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741485 # Number of branches fetched system.cpu.Branches 13741486 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction
system.membus.trans_dist::ReadReq 100925135 # Transaction distribution system.membus.trans_dist::ReadReq 100925136 # Transaction distribution
system.membus.trans_dist::ReadResp 100941054 # Transaction distribution system.membus.trans_dist::ReadResp 100941055 # Transaction distribution
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
system.membus.trans_dist::WriteResp 19849901 # Transaction distribution system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 123744 # Tr
system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290138 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 241861238 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580276 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930618 # Request fanout histogram system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 120930618 # Request fanout histogram system.membus.snoop_fanout::total 120930619 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

98
tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.127293 # Number of seconds simulated sim_seconds 0.127293 # Number of seconds simulated
sim_ticks 127293405500 # Number of ticks simulated sim_ticks 127293406500 # Number of ticks simulated
final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 127293406500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 802256 # Simulator instruction rate (inst/s) host_inst_rate 627920 # Simulator instruction rate (inst/s)
host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) host_op_rate 801678 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1451138855 # Simulator tick rate (ticks/s) host_tick_rate 1135795886 # Simulator tick rate (ticks/s)
host_mem_usage 317568 # Number of bytes of host memory used host_mem_usage 312172 # Number of bytes of host memory used
host_seconds 87.72 # Real time elapsed on the host host_seconds 112.07 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated sim_insts 70373629 # Number of instructions simulated
sim_ops 89847362 # Number of ops (including micro ops) simulated sim_ops 89847363 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
@ -26,16 +26,16 @@ system.physmem.num_reads::total 127812 # Nu
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 62253656 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 64260736 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 42187385 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 42187385 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::writebacks 42187385 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 62253656 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106448121 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 254586811 # number of cpu cycles simulated system.cpu.numCycles 254586813 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70373628 # Number of instructions committed system.cpu.committedInsts 70373629 # Number of instructions committed
system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3311620 # number of times a function call or return occured system.cpu.num_func_calls 3311620 # number of times a function call or return occured
@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 141328474 # nu
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_mem_refs 43422001 # number of memory refs
system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_load_insts 22866262 # Number of load instructions
system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_store_insts 20555739 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles system.cpu.num_busy_cycles 254586812.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 13741485 # Number of branches fetched system.cpu.Branches 13741486 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction
system.cpu.dcache.tags.replacements 155902 # number of replacements system.cpu.dcache.tags.replacements 155902 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 4076.389329 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 1061071000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389329 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@ -352,12 +352,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.replacements 16890 # number of replacements
system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1733.672960 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672960 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
@ -366,14 +366,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 15
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses
system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits
system.cpu.icache.overall_hits::total 78126161 # number of overall hits system.cpu.icache.overall_hits::total 78126162 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
@ -386,12 +386,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 413935000
system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses
@ -438,14 +438,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272
system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 94693 # number of replacements system.cpu.l2cache.tags.replacements 94693 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 30351.005772 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768393 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369526 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy

84
tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
View file

@ -1,40 +1,40 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.099596 # Number of seconds simulated sim_seconds 0.099596 # Number of seconds simulated
sim_ticks 99596491000 # Number of ticks simulated sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1940320 # Simulator instruction rate (inst/s) host_inst_rate 1304038 # Simulator instruction rate (inst/s)
host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1121471108 # Simulator tick rate (ticks/s) host_tick_rate 753711187 # Simulator tick rate (ticks/s)
host_mem_usage 304628 # Number of bytes of host memory used host_mem_usage 298984 # Number of bytes of host memory used
host_seconds 88.81 # Real time elapsed on the host host_seconds 132.14 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated sim_insts 172317410 # Number of instructions simulated
sim_ops 181650341 # Number of ops (including micro ops) simulated sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory
system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 199192983 # number of cpu cycles simulated system.cpu.numCycles 199192984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 172317409 # Number of instructions committed system.cpu.committedInsts 172317410 # Number of instructions committed
system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured system.cpu.num_func_calls 3545028 # number of times a function call or return occured
@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 241970171 # nu
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
system.cpu.num_mem_refs 40540779 # number of memory refs system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300311 # Number of branches fetched system.cpu.Branches 40300312 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Cl
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction
system.membus.trans_dist::ReadReq 217614902 # Transaction distribution system.membus.trans_dist::ReadReq 217614903 # Transaction distribution
system.membus.trans_dist::ReadResp 217637309 # Transaction distribution system.membus.trans_dist::ReadResp 217637310 # Transaction distribution
system.membus.trans_dist::WriteReq 12364287 # Transaction distribution system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
system.membus.trans_dist::WriteResp 12364287 # Transaction distribution system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
system.membus.trans_dist::SoftPFReq 463 # Transaction distribution system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 463 # Tr
system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count) system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 230024466 # Request fanout histogram system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 230024466 # Request fanout histogram system.membus.snoop_fanout::total 230024467 # Request fanout histogram
---------- End Simulation Statistics ---------- ---------- End Simulation Statistics ----------

80
tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
View file

@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.230173 # Number of seconds simulated sim_seconds 0.230173 # Number of seconds simulated
sim_ticks 230173357500 # Number of ticks simulated sim_ticks 230173358500 # Number of ticks simulated
final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1098511 # Simulator instruction rate (inst/s) host_inst_rate 794003 # Simulator instruction rate (inst/s)
host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) host_op_rate 837080 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1471393960 # Simulator tick rate (ticks/s) host_tick_rate 1063522318 # Simulator tick rate (ticks/s)
host_mem_usage 313104 # Number of bytes of host memory used host_mem_usage 308720 # Number of bytes of host memory used
host_seconds 156.43 # Real time elapsed on the host host_seconds 216.43 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated sim_insts 171842484 # Number of instructions simulated
sim_ops 181165370 # Number of ops (including micro ops) simulated sim_ops 181165371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 460346715 # number of cpu cycles simulated system.cpu.numCycles 460346717 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 171842483 # Number of instructions committed system.cpu.committedInsts 171842484 # Number of instructions committed
system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3545028 # number of times a function call or return occured system.cpu.num_func_calls 3545028 # number of times a function call or return occured
@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 242291225 # nu
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
system.cpu.num_mem_refs 40540779 # number of memory refs system.cpu.num_mem_refs 40540779 # number of memory refs
system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_load_insts 27896144 # Number of load instructions
system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_store_insts 12644635 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 40300311 # Number of branches fetched system.cpu.Branches 40300312 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Cl
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction
system.cpu.dcache.tags.replacements 40 # number of replacements system.cpu.dcache.tags.replacements 40 # number of replacements
system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use system.cpu.dcache.tags.tagsinuse 1363.619271 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619271 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
@ -341,12 +341,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.replacements 1506 # number of replacements
system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use system.cpu.icache.tags.tagsinuse 1147.992594 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992594 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
@ -356,14 +356,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 288
system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses
system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits
system.cpu.icache.overall_hits::total 189857001 # number of overall hits system.cpu.icache.overall_hits::total 189857002 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
@ -376,12 +376,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 112371000
system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
@ -428,14 +428,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123
system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use system.cpu.l2cache.tags.tagsinuse 1675.663342 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036747 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588816 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy