ARM: fix some cases where instructions that write to fp reg 15 are accidently branches.
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2 changed files with 6 additions and 6 deletions
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@ -1122,7 +1122,7 @@ def template LoadRegConstructor {{
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#if %(use_uops)d
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#if %(use_uops)d
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assert(numMicroops >= 2);
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assert(numMicroops >= 2);
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uops = new StaticInstPtr[numMicroops];
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uops = new StaticInstPtr[numMicroops];
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if (_dest == INTREG_PC) {
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if (_dest == INTREG_PC && !isFloating()) {
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IntRegIndex wbIndexReg = index;
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IntRegIndex wbIndexReg = index;
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uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
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uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
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_shiftAmt, _shiftType, _index);
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_shiftAmt, _shiftType, _index);
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@ -1156,7 +1156,7 @@ def template LoadRegConstructor {{
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}
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}
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#else
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#else
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if (_dest == INTREG_PC) {
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if (_dest == INTREG_PC && !isFloating()) {
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flags[IsControl] = true;
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flags[IsControl] = true;
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flags[IsIndirectControl] = true;
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flags[IsIndirectControl] = true;
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if (conditional)
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if (conditional)
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@ -1185,7 +1185,7 @@ def template LoadImmConstructor {{
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#if %(use_uops)d
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#if %(use_uops)d
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assert(numMicroops >= 2);
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assert(numMicroops >= 2);
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uops = new StaticInstPtr[numMicroops];
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uops = new StaticInstPtr[numMicroops];
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if (_dest == INTREG_PC) {
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if (_dest == INTREG_PC && !isFloating()) {
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uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
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uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
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_imm);
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_imm);
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uops[0]->setDelayedCommit();
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uops[0]->setDelayedCommit();
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@ -1208,7 +1208,7 @@ def template LoadImmConstructor {{
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uops[1]->setLastMicroop();
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uops[1]->setLastMicroop();
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}
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}
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#else
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#else
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if (_dest == INTREG_PC) {
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if (_dest == INTREG_PC && !isFloating()) {
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flags[IsControl] = true;
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flags[IsControl] = true;
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flags[IsIndirectControl] = true;
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flags[IsIndirectControl] = true;
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if (conditional)
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if (conditional)
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@ -77,7 +77,7 @@ def template DataImmConstructor {{
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}
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}
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}
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}
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if (%(is_branch)s){
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if (%(is_branch)s && !isFloating()){
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flags[IsControl] = true;
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flags[IsControl] = true;
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flags[IsIndirectControl] = true;
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flags[IsIndirectControl] = true;
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if (condCode == COND_AL || condCode == COND_UC)
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if (condCode == COND_AL || condCode == COND_UC)
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@ -117,7 +117,7 @@ def template DataRegConstructor {{
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}
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}
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}
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}
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if (%(is_branch)s){
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if (%(is_branch)s && !isFloating()){
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flags[IsControl] = true;
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flags[IsControl] = true;
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flags[IsIndirectControl] = true;
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flags[IsIndirectControl] = true;
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if (condCode == COND_AL || condCode == COND_UC)
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if (condCode == COND_AL || condCode == COND_UC)
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