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Switch the endianness of data that's forwarded. This is the same sort of problem that was happening when stores went all the way to memory and back.

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--HG--
extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919
This commit is contained in:
Gabe Black 2006-12-16 09:35:09 -05:00
parent 96e5086c81
commit f4f00c5ae9
1 changed files with 6 additions and 0 deletions
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6
src/cpu/o3/lsq_unit.hh
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@ -561,6 +561,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
// Cast this to type T? // Cast this to type T?
data = storeQueue[store_idx].data >> shift_amt; data = storeQueue[store_idx].data >> shift_amt;
// When the data comes from the store queue entry, it's in host
// order. When it gets sent to the load, it needs to be in guest
// order so when the load converts it again, it ends up back
// in host order like the inst expects.
data = TheISA::htog(data);
assert(!load_inst->memData); assert(!load_inst->memData);
load_inst->memData = new uint8_t[64]; load_inst->memData = new uint8_t[64];