From f4a538f8624a3e07ba7a8666ed45ad9bca5e85ed Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Thu, 9 Oct 2014 17:51:56 -0400
Subject: [PATCH] mem: Add packet sanity checks to cache and MSHRs

This patch adds a number of asserts to the cache, checking basic
assumptions about packets being requests or responses.
---
 src/mem/cache/cache.hh      |  2 +-
 src/mem/cache/cache_impl.hh | 13 +++++++++++++
 src/mem/cache/mshr.cc       |  2 ++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 12fb3b0f0..b9a9a7823 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -380,7 +380,7 @@ class Cache : public BaseCache
      * are successfully sent.
      * @param pkt The request that was sent on the bus.
      */
-    void markInService(MSHR *mshr, PacketPtr pkt = 0);
+    void markInService(MSHR *mshr, PacketPtr pkt = NULL);
 
     /**
      * Return whether there are any outstanding misses.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 5cfe7c0cf..24e3eec15 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -107,6 +107,8 @@ template<class TagStore>
 void
 Cache<TagStore>::cmpAndSwap(BlkType *blk, PacketPtr pkt)
 {
+    assert(pkt->isRequest());
+
     uint64_t overwrite_val;
     bool overwrite_mem;
     uint64_t condition_val64;
@@ -149,6 +151,8 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
                                        bool deferred_response,
                                        bool pending_downgrade)
 {
+    assert(pkt->isRequest());
+
     assert(blk && blk->isValid());
     // Occasionally this is not true... if we are a lower-level cache
     // satisfying a string of Read and ReadEx requests from
@@ -247,6 +251,8 @@ template<class TagStore>
 void
 Cache<TagStore>::markInService(MSHR *mshr, PacketPtr pkt)
 {
+    // packet can be either a request or response
+
     markInServiceInternal(mshr, pkt);
 #if 0
         if (mshr->originalCmd == MemCmd::HardPFReq) {
@@ -295,6 +301,9 @@ bool
 Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
                         Cycles &lat, PacketList &writebacks)
 {
+    // sanity check
+    assert(pkt->isRequest());
+
     DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
             pkt->cmdString(), pkt->getAddr(), pkt->getSize());
     if (pkt->req->isUncacheable()) {
@@ -1431,6 +1440,7 @@ typename Cache<TagStore>::BlkType*
 Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
                             PacketList &writebacks)
 {
+    assert(pkt->isResponse());
     Addr addr = pkt->getAddr();
     bool is_secure = pkt->isSecure();
 #if TRACING_ON
@@ -1516,6 +1526,9 @@ Cache<TagStore>::
 doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
                        bool already_copied, bool pending_inval)
 {
+    // sanity check
+    assert(req_pkt->isRequest());
+
     DPRINTF(Cache, "%s for %s address %x size %d\n", __func__,
             req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize());
     // timing-mode snoop responses require a new packet, unless we
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index df3045a2f..79a91da2b 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -247,6 +247,8 @@ MSHR::markInService(PacketPtr pkt)
         popTarget();
         return true;
     }
+
+    assert(pkt != NULL);
     inService = true;
     pendingDirty = (targets.needsExclusive ||
                     (!pkt->sharedAsserted() && pkt->memInhibitAsserted()));