Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5
--HG-- extra : convert_revision : 1fcdbd9d2efc1e0490716de46c81e94f4b28678b
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commit
f3d6ac18e8
1 changed files with 21 additions and 7 deletions
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@ -160,6 +160,8 @@ MemTest::completeRequest(MemReqPtr req, uint8_t *data)
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<< req->size << " bytes at address 0x"
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<< hex << req->paddr << ", value = 0x";
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printData(cerr, req->data, req->size);
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cerr << " @ cycle " << dec << curTick;
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cerr << endl;
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}
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@ -211,6 +213,7 @@ MemTest::tick()
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uint64_t data = random();
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unsigned access_size = random() % 4;
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unsigned cacheable = rand() % 100;
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unsigned probe = rand() % 2;
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MemReqPtr req = new MemReq();
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@ -233,31 +236,42 @@ MemTest::tick()
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uint8_t *result = new uint8_t[8];
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checkMem->access(Read, req->paddr, result, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": initiating read of "
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cerr << name() << ": initiating read "
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<< ((probe)?"probe of ":"access of ")
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<< req->size << " bytes from addr 0x"
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<< hex << req->paddr << " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, result);
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} else {
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req->completionEvent = new MemCompleteEvent(req, result, this);
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cacheInterface->access(req);
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}
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} else {
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// write
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req->cmd = Write;
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memcpy(req->data, &data, req->size);
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checkMem->access(Write, req->paddr, req->data, req->size);
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": initiating write of "
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cerr << name() << ": initiating write "
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<< ((probe)?"probe of ":"access of ")
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<< req->size << " bytes (value = 0x";
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printData(cerr, req->data, req->size);
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cerr << ") to addr 0x"
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<< hex << req->paddr << " at cycle "
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<< dec << curTick << endl;
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}
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if (probe) {
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cacheInterface->probeAndUpdate(req);
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completeRequest(req, NULL);
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} else {
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req->completionEvent = new MemCompleteEvent(req, NULL, this);
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cacheInterface->access(req);
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}
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}
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}
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void
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