Merge ehallnor@zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/ehallnor/m5

--HG--
extra : convert_revision : 1fcdbd9d2efc1e0490716de46c81e94f4b28678b
This commit is contained in:
Erik Hallnor 2003-10-21 01:53:41 -04:00
commit f3d6ac18e8

View file

@ -160,6 +160,8 @@ MemTest::completeRequest(MemReqPtr req, uint8_t *data)
<< req->size << " bytes at address 0x" << req->size << " bytes at address 0x"
<< hex << req->paddr << ", value = 0x"; << hex << req->paddr << ", value = 0x";
printData(cerr, req->data, req->size); printData(cerr, req->data, req->size);
cerr << " @ cycle " << dec << curTick;
cerr << endl; cerr << endl;
} }
@ -211,6 +213,7 @@ MemTest::tick()
uint64_t data = random(); uint64_t data = random();
unsigned access_size = random() % 4; unsigned access_size = random() % 4;
unsigned cacheable = rand() % 100; unsigned cacheable = rand() % 100;
unsigned probe = rand() % 2;
MemReqPtr req = new MemReq(); MemReqPtr req = new MemReq();
@ -233,31 +236,42 @@ MemTest::tick()
uint8_t *result = new uint8_t[8]; uint8_t *result = new uint8_t[8];
checkMem->access(Read, req->paddr, result, req->size); checkMem->access(Read, req->paddr, result, req->size);
if (blockAddr(req->paddr) == traceBlockAddr) { if (blockAddr(req->paddr) == traceBlockAddr) {
cerr << name() << ": initiating read of " cerr << name() << ": initiating read "
<< ((probe)?"probe of ":"access of ")
<< req->size << " bytes from addr 0x" << req->size << " bytes from addr 0x"
<< hex << req->paddr << " at cycle " << hex << req->paddr << " at cycle "
<< dec << curTick << endl; << dec << curTick << endl;
} }
if (probe) {
cacheInterface->probeAndUpdate(req);
completeRequest(req, result);
} else {
req->completionEvent = new MemCompleteEvent(req, result, this); req->completionEvent = new MemCompleteEvent(req, result, this);
cacheInterface->access(req); cacheInterface->access(req);
}
} else { } else {
// write // write
req->cmd = Write; req->cmd = Write;
memcpy(req->data, &data, req->size); memcpy(req->data, &data, req->size);
checkMem->access(Write, req->paddr, req->data, req->size); checkMem->access(Write, req->paddr, req->data, req->size);
if (blockAddr(req->paddr) == traceBlockAddr) { if (blockAddr(req->paddr) == traceBlockAddr) {
cerr << name() << ": initiating write of " cerr << name() << ": initiating write "
<< ((probe)?"probe of ":"access of ")
<< req->size << " bytes (value = 0x"; << req->size << " bytes (value = 0x";
printData(cerr, req->data, req->size); printData(cerr, req->data, req->size);
cerr << ") to addr 0x" cerr << ") to addr 0x"
<< hex << req->paddr << " at cycle " << hex << req->paddr << " at cycle "
<< dec << curTick << endl; << dec << curTick << endl;
} }
if (probe) {
cacheInterface->probeAndUpdate(req);
completeRequest(req, NULL);
} else {
req->completionEvent = new MemCompleteEvent(req, NULL, this); req->completionEvent = new MemCompleteEvent(req, NULL, this);
cacheInterface->access(req); cacheInterface->access(req);
} }
} }
}
void void